參數(shù)資料
型號: C8051F015-TB
廠商: Silicon Laboratories Inc
文件頁數(shù): 166/171頁
文件大?。?/td> 0K
描述: BOARD PROTOTYPING W/C8051F015
標(biāo)準(zhǔn)包裝: 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
13.1.
Power-on Reset
The C8051F000 family incorporates a power supply monitor that holds the MCU in the reset state until VDD rises
above the VRST level during power-up. (See Figure 13.2 for timing diagram, and refer to Table 13.1 for the
Electrical Characteristics of the power supply monitor circuit.) The /RST pin is asserted (low) until the end of the
100ms VDD Monitor timeout in order to allow the VDD supply to become stable.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other reset
flags in the RSTSRC Register are indeterminate. PORSF is cleared by a reset from any other source. Since all
resets cause program execution to begin at the same location (0x0000), software can read the PORSF flag to
determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be
undefined after a power-on reset.
13.2.
Software Forced Reset
Writing a 1 to the PORSF bit forces a Power-On Reset as described in Section 13.1.
Figure 13.2. VDD Monitor Timing Diagram
/RST
t
vol
ts
1.0
2.0
Logic HIGH
Logic LOW
100ms
V
D
2.70
2.40
V
RST
13.3.
Power-fail Reset
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor
will drive the /RST pin low and return the CIP-51 to the reset state (see Figure 13.2). When VDD returns to a level
above VRST, the CIP-51 will leave the reset state in the same manner as that for the power-on reset. Note that even
though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD
dropped below the level required for data retention. If the PORSF flag is set, the data may no longer be valid.
Rev. 1.7
94
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