參數(shù)資料
型號(hào)： C8051F015-TB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 148/171頁
文件大?。?/td> 0K
描述： BOARD PROTOTYPING W/C8051F015
標(biāo)準(zhǔn)包裝： 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 10.4. Interrupt Summary
Interrupt Source
Interrupt
Vector
Priority
Order
Interrupt-Pending Flag
Enable
Reset
0x0000
Top
None
Always enabled
External Interrupt 0 (/INT0)
0x0003
0
IE0 (TCON.1)
EX0 (IE.0)
Timer 0 Overflow
0x000B
1
TF0 (TCON.5)
ET0 (IE.1)
External Interrupt 1 (/INT1)
0x0013
2
IE1 (TCON.3)
EX1 (IE.2)
Timer 1 Overflow
0x001B
3
TF1 (TCON.7)
ET1 (IE.3)
Serial Port (UART)
0x0023
4
RI (SCON.0)
TI (SCON.1)
ES (IE.4)
Timer 2 Overflow (or EXF2)
0x002B
5
TF2 (T2CON.7)
ET2 (IE.5)
Serial Peripheral Interface
0x0033
6
SPIF (SPI0CN.7)
WCOL (SPI0CN.6)
MODF (SPI0CN.5)
RXOVRN (SPI0CN.4)
ESPI0 (EIE1.0)
SMBus Interface
0x003B
7
SI (SMB0CN.3)
ESMB0 (EIE1.1)
ADC0 Window Comparison
0x0043
8
ADWINT (ADC0CN.2)
EWADC0 (EIE1.2)
Programmable Counter Array 0
0x004B
9
CF (PCA0CN.7)
CCFn (PCA0CN.n)
EPCA0 (EIE1.3)
Comparator 0 Falling Edge
0x0053
10
CP0FIF (CPT0CN.4)
ECP0F (EIE1.4)
Comparator 0 Rising Edge
0x005B
11
CP0RIF (CPT0CN.5)
ECP0R (EIE1.5)
Comparator 1 Falling Edge
0x0063
12
CP1FIF (CPT1CN.4)
ECP1F (EIE1.6)
Comparator 1 Rising Edge
0x006B
13
CP1RIF (CPT1CN.5)
ECP1R (EIE1.7)
Timer 3 Overflow
0x0073
14
TF3 (TMR3CN.7)
ET3 (EIE2.0)
ADC0 End of Conversion
0x007B
15
ADCINT (ADC0CN.5)
EADC0 (EIE2.1)
External Interrupt 4
0x0083
16
IE4 (PRT1IF.4)
EX4 (EIE2.2)
External Interrupt 5
0x008B
17
IE5 (PRT1IF.5)
EX5 (EIE2.3)
External Interrupt 6
0x0093
18
IE6 (PRT1IF.6)
EX6 (EIE2.4)
External Interrupt 7
0x009B
19
IE7 (PRT1IF.7)
EX7 (EIE2.5)
Unused Interrupt Location
0x00A3
20
None
Reserved (EIE2.6)
External Crystal OSC Ready
0x00AB
21
XTLVLD (OSCXCN.7)
EXVLD (EIE2.7)
10.4.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low priority
interrupt service routine can be preempted by a high priority interrupt.
A high priority interrupt cannot be
preempted. Each interrupt has an associated interrupt priority bit in an SFR (IP-EIP2) used to configure its priority
level. Low priority is the default. If two interrupts are recognized simultaneously, the interrupt with the higher
priority is serviced first. If both interrupts have the same priority level, a fixed priority order is used to arbitrate.
10.4.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are sampled
and priority decoded each system clock cycle. Therefore, the fastest possible response time is 5 system clock
cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the LCALL to the ISR. If an interrupt is
pending when a RETI is executed, a single instruction is executed before an LCALL is made to service the pending
interrupt.
Therefore, the maximum response time for an interrupt (when no other interrupt is currently being
serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI instruction
followed by a DIV as the next instruction. In this case, the response time is 18 system clock cycles: 1 clock cycle
to detect the interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 4
clock cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher
priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following
instruction.
Rev. 1.7
78
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