參數(shù)資料
型號(hào)： C8051F015-TB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 94/171頁
文件大?。?/td> 0K
描述： BOARD PROTOTYPING W/C8051F015
標(biāo)準(zhǔn)包裝： 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
5.
ADC (12-Bit, C8051F000/1/2/5/6/7 Only)
The ADC subsystem for the C8051F000/1/2/5/6/7 consists of a 9-channel, configurable analog multiplexer
(AMUX), a programmable gain amplifier (PGA), and a 100ksps, 12-bit successive-approximation-register ADC
with integrated track-and-hold and programmable window detector (see block diagram in Figure 5.1). The AMUX,
PGA, Data Conversion Modes, and Window Detector are all configurable under software control via the Special
Function Register’s shown in Figure 5.1. The ADC subsystem (ADC, track-and-hold and PGA) is enabled only
when the ADCEN bit in the ADC Control register (ADC0CN, Figure 5.7) is set to 1. The ADC subsystem is in low
power shutdown when this bit is 0. The Bias Enable bit (BIASE) in the REF0CN register (see Figure 9.2) must be
set to 1 in order to supply bias to the ADC.
Figure 5.1. 12-Bit ADC Functional Block Diagram
12-Bit
SAR
ADC
REF
+
-
AV+
TEMP
SENSOR
12
+
-
+
-
+
-
9-to-1
AMUX
(SE or
DIFF)
AV+
COMB
LOGIC
24
12
ADWINT
ADCEN
SYSCLK
+
-
X
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
TMR3 OV
T2 OV
CNVSTR
ADBUSY(w)
Conver
si
on
St
ar
t
AGND
AMX0CF
AI
N01I
C
AI
N23I
C
AI
N45I
C
AI
N67I
C
AMX0SL
AMXAD0
AMXAD1
AMXAD2
AMXAD3
ADC0CF
AMPG
N0
AMPG
N1
AMPG
N2
ADCSC0
ADCSC1
ADCSC2
ADC0CN
ADLJ
ST
ADWI
NT
ADSTM0
ADSTM1
ADBUSY
ADCINT
ADCTM
ADCEN
ADC0L
ADC0H
ADC0LTL
ADC0LTH
ADC0GTL
ADC0GTH
5.1.
Analog Multiplexer and PGA
Eight of the AMUX channels are available for external measurements while the ninth channel is internally
connected to an on-board temperature sensor (temperature transfer function is shown in Figure 5.3). Note that the
PGA gain is applied to the temperature sensor reading. AMUX input pairs can be programmed to operate in either
the differential or single-ended mode. This allows the user to select the best measurement technique for each input
channel, and even accommodates mode changes “on-the-fly”. The AMUX defaults to all single-ended inputs upon
reset. There are two registers associated with the AMUX: the Channel Selection register AMX0SL (Figure 5.5),
and the Configuration register AMX0CF (Figure 5.4). The table in Figure 5.5 shows AMUX functionality by
channel for each possible configuration. The PGA amplifies the AMUX output signal by an amount determined by
the AMPGN2-0 bits in the ADC Configuration register, ADC0CF (Figure 5.6).
The PGA can be software-
programmed for gains of 0.5, 1, 2, 4, 8 or 16. It defaults to unity gain on reset.
29
Rev. 1.7
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