參數(shù)資料
型號: C8051F015-TB
廠商: Silicon Laboratories Inc
文件頁數(shù): 50/171頁
文件大?。?/td> 0K
描述: BOARD PROTOTYPING W/C8051F015
標準包裝: 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 19.5. TMOD: Timer Mode Register
R/W
Reset Value
GATE1
C/T1
T1M1
T1M0
GATE0
C/T0
T0M1
T0M0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x89
Bit7:
GATE1: Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND /INT1 = logic level one.
Bit6:
C/T1: Counter/Timer 1 Select.
0: Timer Function: Timer 1 incremented by clock defined by T1M bit (CKCON.4).
1: Counter Function: Timer 1 incremented by high-to-low transitions on external input pin
(T1).
Bits5-4: T1M1-T1M0: Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
T1M1
T1M0
Mode
0
Mode 0: 13-bit counter/timer
0
1
Mode 1: 16-bit counter/timer
1
0
Mode 2: 8-bit counter/timer with auto-reload
1
Mode 3: Timer 1 Inactive/stopped
Bit3:
GATE0: Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of /INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND /INT0 = logic level one.
Bit2:
C/T0: Counter/Timer Select.
0: Timer Function: Timer 0 incremented by clock defined by T0M bit (CKCON.3).
1: Counter Function: Timer 0 incremented by high-to-low transitions on external input pin
(T0).
Bits1-0: T0M1-T0M0: Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
T0M1
T0M0
Mode
0
Mode 0: 13-bit counter/timer
0
1
Mode 1: 16-bit counter/timer
1
0
Mode 2: 8-bit counter/timer with auto-reload
1
Mode 3: Two 8-bit counter/timers
143
Rev. 1.7
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