參數(shù)資料
型號: C8051F015-TB
廠商: Silicon Laboratories Inc
文件頁數(shù): 60/171頁
文件大小: 0K
描述: BOARD PROTOTYPING W/C8051F015
標準包裝: 1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
19.3.
Timer 3
Timer 3 is a 16-bit timer formed by the two 8-bit SFRs, TMR3L (low byte) and TMR3H (high byte). The input for
Timer 3 is the system clock (divided by either one or twelve as specified by the Timer 3 Clock Select bit T3M in the
Timer 3 Control Register TMR3CN). Timer 3 is always configured as an auto-reload timer, with the reload value
held in the TMR3RLL (low byte) and TMR3RLH (high byte) registers. Timer 3 can be used to start an ADC Data
Conversion, for SMBus timing (see Section 16.5), or as a general-purpose timer. Timer 3 does not have a counter
mode.
Figure 19.19. Timer 3 Block Diagram
TMR3L
TMR3H
TR3
SYSCLK
12
0
1
TCLK
TMR3RLL TMR3RLH
Reload
Interrupt
TMR3CN
TR3
T3M
TF3
T3M
TOE
SCL
(from SMBus)
(to ADC)
Crossbar
Figure 19.20. TMR3CN: Timer 3 Control Register
R/W
Reset Value
TF3
-
TR3
T3M
-
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0x91
Bit7:
TF3: Timer3 Overflow Flag.
Set by hardware when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3
interrupt is enabled, setting this bit causes the CPU to vector to the Timer 3 Interrupt
service routine. This bit is not automatically cleared by hardware and must be cleared by
software.
Bits6-3: UNUSED. Read = 0000b, Write = don’t care.
Bit2:
TR3: Timer 3 Run Control.
This bit enables/disables Timer 3.
0: Timer 3 disabled.
1: Timer 3 enabled.
Bit1:
T3M: Timer 3 Clock Select.
This bit controls the division of the system clock supplied to Counter/Timer 3.
0: Counter/Timer 3 uses the system clock divided by 12.
1: Counter/Timer 3 uses the system clock.
Bit0:
UNUSED. Read = 0, Write = don’t care.
Rev. 1.7
152
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