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| 型號(hào)： | C8051F015-TB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 167/171頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD PROTOTYPING W/C8051F015 |
| 標(biāo)準(zhǔn)包裝： | 1 |
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
13.4.
External Reset
The external /RST pin provides a means for external circuitry to force the MCU into a reset state. Asserting an
active-low signal on the /RST pin will cause the MCU to enter the reset state. Although there is a weak internal
pullup, it may be desirable to provide an external pull-up and/or decoupling of the /RST pin to avoid erroneous
noise-induced resets. The MCU will remain in reset until at least 12 clock cycles after the active-low /RST signal is
removed. The PINRSF flag (RSTSRC.0) is set on exit from an external reset. The /RST pin is also 5V tolerant.
13.5.
Missing Clock Detector Reset
The Missing Clock Detector is essentially a one-shot circuit that is triggered by the MCU system clock. If the
system clock goes away for more than 100
s, the one-shot will time out and generate a reset. After a Missing Clock
Detector reset, the MCDRSF flag (RSTSRC.2) will be set, signifying the MSD as the reset source; otherwise, this
bit reads 0. The state of the /RST pin is unaffected by this reset. Setting the MSCLKE bit in the OSCICN register
(see Figure 14.2) enables the Missing Clock Detector.
13.6.
Comparator 0 Reset
Comparator 0 can be configured as an active-low reset input by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator 0 should be enabled using CPT0CN.7 (see Figure 8.3) at least 20
s prior to writing to C0RSEF to
prevent any turn-on chatter on the output from generating an unwanted reset. When configured as a reset, if the
non-inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the MCU is put into the
reset state. After a Comparator 0 Reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying Comparator 0 as the
reset source; otherwise, this bit reads 0. The state of the /RST pin is unaffected by this reset. Also, Comparator 0
can generate a reset with or without the system clock.
13.7.
External CNVSTR Pin Reset
The external CNVSTR signal can be configured as an active-low reset input by writing a 1 to the CNVRSEF flag
(RSTSRC.6). The CNVSTR signal can appear on any of the P0, P1, or P2 I/O pins as described in Section 15.1.
(Note that the Crossbar must be configured for the CNVSTR signal to be routed to the appropriate Port I/O.) The
Crossbar should be configured and enabled before the CNVRSEF is set to configure CNVSTR as a reset source.
When configured as a reset, CNVSTR is active-low and level sensitive. After a CNVSTR reset, the CNVRSEF flag
(RSTSRC.6) will read 1 signifying CNVSTR as the reset source; otherwise, this bit reads 0. The state of the /RST
pin is unaffected by this reset.
13.8.
Watchdog Timer Reset
The MCU includes a programmable Watchdog Timer (WDT) running off the system clock. The WDT will force
the MCU into the reset state when the watchdog timer overflows. To prevent the reset, the WDT must be restarted
by application software before the overflow occurs. If the system experiences a software/hardware malfunction
preventing the software from restarting the WDT, the WDT will overflow and cause a reset. This should prevent
the system from running out of control.
The WDT is automatically enabled and started with the default maximum time interval on exit from all resets. If
desired the WDT can be disabled by system software or locked on to prevent accidental disabling. Once locked, the
WDT cannot be disabled until the next system reset. The state of the /RST pin is unaffected by this reset.
95
Rev. 1.7
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