參數(shù)資料
型號： COP8CBR9KMT8
廠商： National Semiconductor
文件頁數(shù)： 47/111頁
文件大?。?/td> 0K
描述： IC MCU EEPROM 8BIT 32K 56-TSSOP
標(biāo)準(zhǔn)包裝： 34
系列： COP8™ 8C
核心處理器： COP8
芯體尺寸： 8-位
速度： 20MHz
連通性： Microwire/Plus（SPI），UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 49
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-TFSOP（0.240"，6.10mm 寬）
包裝： 管件
其它名稱： *COP8CBR9KMT8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Erase a page of flash memory at a specified address.
Read a byte from a specified address.
Write a byte to a specified address.
Copy a block of data from RAM into flash program memory.
Copy a block of data from program flash memory to RAM.
The following table lists the User ISP/Virtual E2 commands, required parameters and return data, if
applicable. The command entry point is used as an argument to the JSRB instruction. Table 5-11 lists the
Ram locations and Peripheral Registers, used for User ISP and Virtual E2, and their expected contents.
Please refer to the COP8 FLASH ISP User Manual for additional information and programming examples
on the use of User ISP and Virtual E2.
Table 5-10. User ISP/Virtual E2 Entry Points
Command/
Command
Function
Parameters
Return Data
Label
Entry Point
cpgerase
Page Erase
0x17
Register ISPADHI is loaded by the user with N/A (A page of memory beginning at
the high byte of the address.
ISPADHI, ISPADLO will be erased)
Register ISPADLO is loaded by the user
with the low byte of the address.
cmserase
Mass Erase
0x1A
Accumulator A contains the confirmation
N/A (The entire Flash Memory will be
key 0x55.
erased)
creadbf
Read Byte
0x11
Register ISPADHI is loaded by the user with Data Byte in Register ISPRD.
the high byte of the address.
Register ISPADLO is loaded by the user
with the low byte of the address.
cblockr
Block Read
0x26
Register ISPADHI is loaded by the user with n Data Bytes, Data will be returned
the high byte of the address.
beginning at a location pointed to by the
Register ISPADLO is loaded by the user
RAM address in X.
with the low byte of the address.
X pointer contains the beginning RAM
address where the result(s) will be returned.
Register BYTECOUNTLO contains the
number of n bytes to read (0
≤ n ≤ 255). It is
up to the user to setup the segment register.
cwritebf
Write Byte
0x14
Register ISPADHI is loaded by the user with N/A
the high byte of the address.
Register ISPADLO is loaded by the user
with the low byte of the address.
Register ISPWR contains the Data Byte to
be written.
cblockw
Block Write
0x23
Register ISPADHI is loaded by the user with N/A
the high byte of the address.
Register ISPADLO is loaded by the user
with the low byte of the address.
Register BYTECOUNTLO contains the
number of n bytes to write (0
≤ n ≤ 16).
The combination of the BYTECOUNTLO
and the ISPADLO registers must be set
such that the operation will not cross a 64
byte boundary.
X pointer contains the beginning RAM
address of the data to be written.
It is up to the user to setup the segment
register.
exit
EXIT
0x62
N/A
N/A (Device will Reset)
uwisp
MICROWIRE/
0x00
N/A
N/A (Device will be in MICROWIRE/PLUS
PLUS
ISP Mode. Must be terminated by
ISP Start
MICROWIRE/PLUS ISP EXIT command
which will Reset the device)
40
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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