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參數(shù)資料
| 型號(hào)： | COP8CBR9KMT8 |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 85/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU EEPROM 8BIT 32K 56-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 34 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 49 |
| 程序存儲(chǔ)器容量： | 32KB（32K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 包裝： | 管件 |
| 其它名稱： | *COP8CBR9KMT8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
Upon Reset, all pending bits, individual enable bits, and the GIE bit are reset to zero. Thus, a maskable
interrupt condition cannot trigger an interrupt until the program enables it by setting both the GIE bit and
the individual enable bit. When enabling an interrupt, the user should consider whether or not a previously
activated (set) pending bit should be acknowledged. If, at the time an interrupt is enabled, any previous
occurrences of the interrupt should be ignored, the associated pending bit must be reset to zero prior to
enabling the interrupt. Otherwise, the interrupt may be simply enabled; if the pending bit is already set, it
will immediately trigger an interrupt. A maskable interrupt is active if its associated enable and pending
bits are set.
An interrupt is an asychronous event which may occur before, during, or after an instruction cycle. Any
interrupt which occurs during the execution of an instruction is not acknowledged until the start of the next
normally executed instruction. If the next normally executed instruction is to be skipped, the skip is
performed before the pending interrupt is acknowledged.
At the start of interrupt acknowledgment, the following actions occur:
1. The GIE bit is automatically reset to zero, preventing any subsequent maskable interrupt from
interrupting the current service routine. This feature prevents one maskable interrupt from interrupting
another one being serviced.
2. The address of the instruction about to be executed is pushed onto the stack.
3. The program counter (PC) is loaded with 00FF Hex, causing a jump to that program memory location.
The device requires seven instruction cycles to perform the actions listed above.
If the user wishes to allow nested interrupts, the interrupts service routine may set the GIE bit to 1 by
writing to the PSW register, and thus allow other maskable interrupts to interrupt the current service
routine. If nested interrupts are allowed, caution must be exercised. The user must write the program in
such a way as to prevent stack overflow, loss of saved context information, and other unwanted
conditions.
The interrupt service routine stored at location 00FF Hex should use the VIS instruction to determine the
cause of the interrupt, and jump to the interrupt handling routine corresponding to the highest priority
enabled and active interrupt. Alternately, the user may choose to poll all interrupt pending and enable bits
to determine the source(s) of the interrupt. If more than one interrupt is active, the user's program must
decide which interrupt to service.
Within a specific interrupt service routine, the associated pending bit should be cleared. This is typically
done as early as possible in the service routine in order to avoid missing the next occurrence of the same
type of interrupt event. Thus, if the same event occurs a second time, even while the first occurrence is
still being serviced, the second occurrence will be serviced immediately upon return from the current
interrupt routine.
An interrupt service routine typically ends with an RETI instruction. This instruction set the GIE bit back to
1, pops the address stored on the stack, and restores that address to the program counter. Program
execution then proceeds with the next instruction that would have been executed had there been no
interrupt. If there are any valid interrupts pending, the highest-priority interrupt is serviced immediately
upon return from the previous interrupt.
NOTE
While executing from the Boot ROM for ISP or virtual E2 operations, the hardware will
disable interrupts from occurring. The hardware will leave the GIE bit in its current state, and
if set, the hardware interrupts will occur when execution is returned to Flash Memory.
Subsequent interrupts, during ISP operation, from the same interrupt source will be lost.
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
75
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| COP8CCE9 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS Flash Microcontroller with 8k Memory, Virtual EEPROM, 10-Bit A/D and Brownout Reset |
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