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| 型號： | COP8CBR9KMT8 |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 77/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU EEPROM 8BIT 32K 56-TSSOP |
| 標準包裝： | 34 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 49 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 包裝： | 管件 |
| 其它名稱： | *COP8CBR9KMT8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
5.13.9 DIAGNOSTIC
Bits CHL0 and CHL1 in the ENU register provide a loopback feature for diagnostic testing of the USART.
When both bits are set to one, the following occurs: The receiver input pin (RDX) is internally connected to
the transmitter output pin (TDX); the output of the Transmitter Shift Register is “l(fā)ooped back” into the
Receive Shift Register input. In this mode, data that is transmitted is immediately received. This feature
allows the processor to verify the transmit and receive data paths of the USART.
Note that the framing format for this mode is the nine bit format; one Start bit, nine data bits, and one or
two Stop bits. Parity is not generated or verified in this mode.
5.13.10 ATTENTION MODE
The USART Receiver section supports an alternate mode of operation, referred to as ATTENTION Mode.
This mode of operation is selected by the ATTN bit in the ENUR register. The data format for transmission
must also be selected as having nine Data bits and either one or two Stop bits.
The ATTENTION mode of operation is intended for use in networking the device with other processors.
Typically in such environments the messages consists of device addresses, indicating which of several
destinations should receive them, and the actual data. This Mode supports a scheme in which addresses
are flagged by having the ninth bit of the data field set to a 1. If the ninth bit is reset to a zero the byte is a
Data byte.
While in ATTENTION mode, the USART monitors the communication flow, but ignores all characters until
an address character is received. Upon receiving an address character, the USART signals that the
character is ready by setting the RBFL flag, which in turn interrupts the processor if USART Receiver
interrupts are enabled. The ATTN bit is also cleared automatically at this point, so that data characters as
well as address characters are recognized. Software examines the contents of the RBUF and responds by
deciding either to accept the subsequent data stream (by leaving the ATTN bit reset) or to wait until the
next address character is seen (by setting the ATTN bit again).
Operation of the USART Transmitter is not affected by selection of this Mode. The value of the ninth bit to
be transmitted is programmed by setting XBIT9 appropriately. The value of the ninth bit received is
obtained by reading RBIT9. Since this bit is located in ENUR register where the error flags reside, a bit
operation on it will reset the error flags.
5.13.11 BREAK GENERATION
To generate a line break, the user software should set the BRK bit in the ENUI register. This will force the
TDX pin to 0 and hold it there until the BRK bit is reset.
5.14 A/D Converter
This device contains a 16-channel, multiplexed input, successive approximation, 10 bit Analog-to-Digital
Converter. Pins AVCC and AGND are used for the voltage reference.
5.14.1 OPERATING MODES
It supports both Single Ended and Differential modes of operation.
Two specific analog channel selection modes are supported. These are as follows:
1. Allow any specific channel to be selected at one time. The A/D Converter performs the specific
conversion requested and stops.
2. Allow any differential channel pair to be selected at one time. The A/D Converter performs the specific
differential conversion requested and stops.
In both Single Ended and Differential modes, there is the capability to connect the analog multiplexor
output and A/D converter input to external pins. This provides the ability to externally connect a common
filter/signal conditioning circuit for the A/D Converter.
68
Functional Description
Copyright 2000–2013, Texas Instruments Incorporated
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