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| 型號(hào)： | COP8CBR9KMT8 |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 92/111頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU EEPROM 8BIT 32K 56-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 34 |
| 系列： | COP8™ 8C |
| 核心處理器： | COP8 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | Microwire/Plus（SPI），UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 49 |
| 程序存儲(chǔ)器容量： | 32KB（32K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 1K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 包裝： | 管件 |
| 其它名稱： | *COP8CBR9KMT8 |
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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
should return to execute the VIS instruction. This is particularly useful when exiting long interrupt
service routines if the time between interrupts is short. In this case the RETI instruction would only be
executed when the default VIS routine is reached.
3. While executing from the Boot ROM for ISP or virtual E2 operations, the hardware will disable
interrupts from occurring. The hardware will leave the GIE bit in its current state, and if set, the
hardware interrupts will occur when execution is returned to Flash Memory. Subsequent interrupts,
during ISP operation, from the same interrupt source will be lost.
5.16 WATCHDOG/Clock Monitor
The devices contain a user selectable WATCHDOG and clock monitor. The following section is applicable
only if the WATCHDOG feature has been selected in the Option register. The WATCHDOG is designed to
detect the user program getting stuck in infinite loops resulting in loss of program control or “runaway”
programs.
The WATCHDOG logic contains two separate service windows. While the user programmable upper
window selects the WATCHDOG service time, the lower window provides protection against an infinite
program loop that contains the WATCHDOG service instruction. The WATCHDOG uses the Idle Timer
(T0) and thus all times are measured in Idle Timer Clocks.
The Clock Monitor is used to detect the absence of a clock or a very slow clock below a specified rate on
tC.
The WATCHDOG consists of two independent logic blocks: WD UPPER and WD LOWER. WD UPPER
establishes the upper limit on the service window and WD LOWER defines the lower limit of the service
window.
Servicing the WATCHDOG consists of writing a specific value to a WATCHDOG Service Register named
WDSVR which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-
bit Window Select, a 5-bit Key Data field, and the 1-bit Clock Monitor Select field. Table 5-26 shows the
WDSVR register.
Table 5-26. WATCHDOG Service Register (WDSVR)
Window Select
Key Data
Clock Monitor
X
0
1
0
Y
7
6
5
4
3
2
1
0
The lower limit of the service window is fixed at 2048 Idle Timer Clocks. Bits 7 and 6 of the WDSVR
register allow the user to pick an upper limit of the service window.
Table 5-27 shows the four possible combinations of lower and upper limits for the WATCHDOG service
window. This flexibility in choosing the WATCHDOG service window prevents any undue burden on the
user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the 5-bit Key Data field. The key data is fixed at
01100. Bit 0 of the WDSVR Register is the Clock Monitor Select bit.
Table 5-27. WATCHDOG Service Window Select
Clock
Service Window
WDSVR
Monitor
for High Speed Mode
for Dual Clock & Low Speed Modes
Bit 7
Bit 6
Bit 0
(Lower-Upper Limits)
0
X
2048-8k tC Cycles
2048-8k Cycles of 32 kHz Clk
0
1
X
2048-16k tC Cycles
2048-16k Cycles of LS 32 kHz Clk
1
0
X
2048-32k tC Cycles
2048-32k Cycles of LS 32 kHz Clk
1
X
2048-64k tC Cycles
2048-64k Cycles of LS 32 kHz Clk
X
0
Clock Monitor Disabled
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
81
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