參數(shù)資料
型號： CR16HCS5VJE8
英文描述： Microcontroller
中文描述： 微控制器
文件頁數(shù)： 112/157頁
文件大小： 1256K
代理商： CR16HCS5VJE8
www.national.com
112
GM[28:15]
The following are the bits for the GMSKB regis-
ter.
5
4
GM[28:18]
RTR
0
r/w
GM[14:0]
The following are the bits for the GMSKX regis-
ter.
For all GMSKB and GMSKX register bits, the following ap-
plies:
— “0” is the incoming identifier bit must match the corre-
sponding bit in the message buffer identifier register.
— “1” accept “1” or “0” (“don’t care”) of the incoming ID bit
independent from the corresponding bit in the mes-
sage buffer ID registers. The corresponding ID bit in
the message buffer will be overwritten by the incoming
identifier bits.
When an extended frame is received from the CAN bus, all
Global Mask bits GM28 through GM0, IDE, RTR and XRTR
are used to mask the incoming message.
During the reception of standard frames only the Global
Mask bits GM28 to GM18, RTR and IDE are utilized.
Global Mask
GM[28:1
8]
standard frame
ID[10:0]
RTR
extended frame ID[28:18]
SRR IDE
20.9.11 Basic Mask Registers (BMSK — BMSKB and
BMSKX)
The two registers BMSKB and BMSKX allow to mask the
buffer 14, or “don’t care” the incoming extended/standard
identifier bits, RTR/XRTR and IDE. Throughout this docu-
ment, the two 16-bit registers BMSKB and BMSKX are refer-
enced to as a 32-bit register BMSK.
BM[28:15]
The following are the bits for the BMSKB regis-
ter.
BM[14:0]
The following are the bits for the BMSKX regis-
ter.
1
BM[14:0]
0
r/w
For all BMSKB and BMSKX register bits the following ap-
plies:
— “0” incoming identifier bit must match the correspond-
ing bit in the message buffer identifier register.
— “1” accept “1” or “0” (“don’t care”) of the incoming ID bit
independent from the corresponding bit in the mes-
sage buffer ID registers. The corresponding ID bit in
the message buffer will be overwritten by the incoming
identifier bits.
When an extended frame is received from the CAN bus all
Basic Mask bits BM28 through BM0, IDE, RTR and XRTR
are used to mask the incoming message.
During the reception of standard frames only the Basic Mask
bits BM28 to BM18, RTR and IDE are utilized.
Basic Mask
BM[28:1
8]
standard
frame
extended
frame
20.9.12 CAN Interrupt Enable Register (CIEN)
The CAN Interrupt Enable (CIEN) register enables the trans-
mit/receive interrupts of the message buffers 0 through 14 as
well as the CAN Error Interrupt.
15
14
EIEN
0
r/w
EIEN
Error Interrupt Enable. This bit allows the
CR16CAN to interrupt the CPU if any kind of
CAN receive/transmit errors are detected. This
means any error status change in the error
counter registers REC/TEC is able to generate
an error interrupt if EIEN is enabled.
“0”
The error interrupt is disabled and no error
interrupt will be generated.
“1”
The error interrupt is enabled and a
change in REC/TEC will cause an inter-
rupt to be generated.
Buffer Interrupt Enable. The IEN[14:0] allow
the user to enable/disable interrupt source for
each of the message buffers i.e., IEN14 config-
ures buffer14 and IEN0 configures buffer0.
“0”
buffer as interrupt source disabled
“1”
buffer as interrupt source enabled
IEN[14:0]
15
3
2
0
IDE
GM[17:15]
15
1
0
GM[14:0]
XRTR
0
r/w
RTR
a
a.
the RTR bit has a different position in standard and
extended frames
— for standard frames the GMSK_RTR bit is used to
mask this bit
— for extended frames the GMSK_XRTR bit is used to
mask this
bit
IDE
GM[17:0]
XRT
R
IDE
unused
ID[17:0]
RTR
15
5
4
3
2
0
BM[28:18]
RTR
0
r/w
IDE
BM[17:15]
15
0
XRTR
RTR
a
a. the RTR bit has a different position in standard and
extended frames
— for standard frames the BMSK_RTR bit is used to
mask this bit
— for extended frames the BMSK_XRTR bit is used to
mask this bit
IDE BM[17:0]
XRTR
ID[10:0]
RTR
IDE
unused
ID[28:18]
SRR
IDE
ID[17:0]
RTR
0
IEN[14:0]
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