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參數(shù)資料
| 型號： | CR16HCS5VJE8 |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 5/157頁 |
| 文件大小： | 1256K |
| 代理商： | CR16HCS5VJE8 |
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3.0
Device Overview
TheCR16MCS9/CR16MCS5 and CR16HCS9/CR16HCS5
are complete microcomputers with all system timing, inter-
rupt logic, program memory, data memory, and I/O ports in-
cluded on-chip, making it well-suited to a wide range of
embedded controller applications.
3.1
The CR16MCS9/CR16MCS5 and CR16HCS9/CR16HCS5
uses a CR16B CPU core module. This is the same core used
in other CompactRISC family member designs, like DECT or
GSM chipsets.
The high performance of the CPU core results from the im-
plementation of a pipelined architecture with a two-bytes-per-
cycle pipelined system bus. As a result, the CPU can support
a peak execution rate of one instruction per clock cycle.
Compared with conventional RISC processors, the devices
differ in the following ways:
— The CPU core can use on-chip rather than external
memory. This eliminates the need for large and com-
plex bus interface units.
— Most instructions are 16 bits, so all basic instructions
are just two bytes long. Additional bytes are sometimes
required for immediate values, so instructions can be
two or four bytes long.
— Non-aligned word access is allowed. Each instruction
can operate on 8-bit or 16-bit data.
— The devices are designed to operate with a clock rate
in the 10 to 24 MHz range rather than 100 MHz or
more. Most embedded systems face EMI and noise
constraints that limit clock speed to these lower rang-
es. A lower clock speed means a simpler, less costly
silicon implementation.
— The instruction pipeline uses three stages. A smaller
pipeline eliminates the need for costly branch predic-
tion mechanisms and bypass registers, while maintain-
ing adequate performance for typical embedded
controller applications.
For more information, please refer to the CR16B Program-
mer’s Reference Manual, Literature #: 633150.
CR16B CPU CORE
3.2
The CompactRISC architecture supports a uniform linear ad-
dress space of 2 megabytes. The CR16MCS9/CR16MCS5
and CR16HCS9/CR16HCS5 implementation of this architec-
ture uses only the lowest 128K bytes of address space. Four
types of on-chip memory occupy specific intervals within this
address space:
64K bytes of flash EEPROM program memory (100K cy-
cles)
48K bytes ROM programm memory version available also
(100K cycles)
3K bytes of static RAM
2K bytes of EEPROM data memory with low endurance
(25K cycles)
128 bytes with high endurance (100K cycles)
1.5K bytes flash EEPROM memory for ISP code
MEMORY
The 3K bytes of static RAM are used for temporary storage
of data and for the program stack and interrupt stack. Read
and write operations can be byte-wide or word-wide, depend-
ing on the instruction executed by the CPU. Each memory
access requires one clock cycle; no wait cycles or hold cycles
are required.
There are two types of flash EEPROM data memory storage.
The 2K bytes of EEPROM data memory with low endurance
(25K cycles) and 128 bytes of flash EEPROM data memory
with high endurance (100K cycles) are used for non-volatile
storage of data, such as configuration settings entered by the
end-user.
The 64K bytes of flash EEPROM program memory are used
to store the application program. It has security features to
prevent unintentional programming and to prevent unautho-
rized access to the program code. This memory can be pro-
grammed with a device external programming unit or with the
CR16MCS9/CR16MCS5 and CR16HCS9/CR16HCS5 in-
stalled in the application system (in-system programming).
There is a factory programmed boot memory used to store
In-System-Programming (ISP) code. (This code allows pro-
gramming of the program memory via one of the USART in-
terfaces in the final application.)
For flash EEPROM program and data memory, the
CR16MCS9/CR16MCS5 and CR16HCS9/CR16HCS5 inter-
nally generates the necessary voltages for programming. No
additional power supply is required.
3.3
The CCR16MCS9/CR16MCS5 and CR16HCS9/CR16HCS5
devices havs 56 software-configurable I/O pins, organized
into seven 8-pin ports called Port B, Port C, Port F, Port G,
Port H, Port I, and Port L. Each pin can be configured to op-
erate as a general-purpose input or general-purpose output.
In addition, many I/O pins can be configured to operate as a
designated input or output for an on-chip peripheral module
such as the USART, timer, A/D converter, or MICROWIRE/
SPI interface.
The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, push-
pull output, weak pull-up input, or high-impedance input.
INPUT/OUTPUT PORTS
3.4
The Bus Interface Unit (BIU) controls the interface between
the on-chip modules to the internal core bus. It determines
the configured parameters for bus access (such as the num-
ber of wait states for memory access) and issues the appro-
priate bus signals for each requested access.
The BIU uses a set of control registers to determine how
many wait states and hold states are to be used when ac-
cessing flash EEPROM program memory, ISP memory and
the I/O area (Port B and Port C). Upon start-up the configu-
ration registers are set for slowest possible memory access.
To achieve fastest possible program execution, appropriate
values should be programmed. These settings vary with the
clock frequency and the type of on-chip device being access-
ed.
BUS INTERFACE UNIT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CR16HCS9VJE7Y | Microcontroller |
| CR16HCS9VJE8Y | Microcontroller |
| CR16HCT5 | |
| CR16HCT5VJE7Y | Microcontroller |
| CR16HCT5VJE8Y | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CR16HCS5VJE8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCS5VJI8 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9VJE0 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9VJE1 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
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