- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366891 > CR16HCS5VJE8 Microcontroller PDF資料下載
參數(shù)資料
| 型號(hào)： | CR16HCS5VJE8 |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁(yè)數(shù)： | 20/157頁(yè) |
| 文件大?。?/td> | 1256K |
| 代理商： | CR16HCS5VJE8 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)當(dāng)前第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)
www.national.com
20
cycles used for each memory access, ranging
from 00 binary for no Thold cycles to 11 binary
for three Thold clock cycles. These bits are ig-
nored if the SZCFG0.FRE bit is set to 1.
Bus Width.
This bit defines the bus width of the zone.
If cleared to 0, a bus width of 8-bit is used.
if set to 1, a bus width of 16-bit is used.
For the device a bus width of 16-bit needs to be
set.
Fast Read Enable
This bit enables (1) or disables (0) fast read bus
cycles. A fast read operation takes one clock
cycle. A normal read operation takes at least
two clock cycles.
Post Idle.
An idle cycle follows the current bus cycle,
when the next bus cycle accesses a different
zone.
If cleared to 0, no idle cycle is inserted.
If set to 1, one idle cycle is inserted.
The IPST bit can be cleared to 0, as no idle cy-
cles are required for on-chip accesses.
Preliminary Idle.
An idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a dif-
ferent zone.
If cleared to 0, no idle cycle is inserted.
If set to 1, one idle cycle is inserted.
The IPRE bit can be cleared to 0, as no idle cy-
cles are required for on-chip accesses.
Note:
Reserved bits must be cleared to 0 when the CPU
writes to the register.
BW
FRE
IPST
IPRE
8.3
The number of wait cycles and hold cycles inserted into a bus
cycle depends on whether it is a read or write operation, the
type of memory or I/O being accessed, and the control regis-
ter settings.
WAIT AND HOLD STATES USED
8.3.1
When the CPU accesses the flash EEPROM program mem-
ory (address ranges 0000-BFFF and 1C000-1FFFF), the
number of added wait and hold cycles depends on the type
of access and the BIU register settings.
In fast read mode (SZCFG0.FRE=1), a read operation is a
single cycle access. This limits the maximum CPU operating
frequency to either 10 MHz or 20 MHz (see Section 9.1.5).
For a read operation in normal read mode (SZCFG0.FRE=0),
the number of inserted wait cycles is one plus the value writ-
ten to the SZCFG0.WAIT field. The number in this field can
range from zero to seven, so the total number of wait cycles
can range from one to eight. The number of inserted hold cy-
cles is equal to the value written to the SCCFG0.HOLD field,
which can range from zero to three.
For a write operation in fast read mode (SZCFG0.FRE=1),
the number of inserted wait cycles is one. No hold cycles are
used.
Flash EEPROM Program Memory
For a write operation normal read mode (SZCFG0.FRE=0),
the number of wait cycles is equal to the value written to the
SZCFG0. WAIT field plus one (in the late write mode) or two
(in the early write mode). The number of inserted hold cycles
is equal to the value written to the SCCFG0.HOLD field,
which can range from zero to three.
Writing to the flash EEPROM program memory is a Flash
programming operation that requires some additional steps,
as explained in Section 9.3.
8.3.2
Read and write accesses to on-chip RAM is performed within
a single cycle, regardless of the BIU settings.
RAM Memory
8.3.3
There is either no wait state or one wait state used when the
CPU accesses the EEPROM data memory (address F000-
F27F hex). The number of required wait states (zero or one)
depends on the CPU clock frequency and operating mode,
and is controlled by programming of the DMCSR.ZEROWS
bit in the MCFG register, as explained in Section 9.3. No hold
cycles are used.
EEPROM Data Memory
8.3.4
When the CPU accesses on-chip peripherals in the range of
F800-FAFF hex and FC00-FFFF hex, one wait cycle and one
preliminary idle cycle is used. No hold cycles are used.
The IOCFG register determines the access timing for the ad-
dress range FB00-FB16 hex (Ports B and Port C).
Accesses to Peripheral
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CR16HCS9VJE7Y | Microcontroller |
| CR16HCS9VJE8Y | Microcontroller |
| CR16HCT5 | |
| CR16HCT5VJE7Y | Microcontroller |
| CR16HCT5VJE8Y | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CR16HCS5VJE8Y | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microcontroller |
| CR16HCS5VJI8 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9VJE0 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
| CR16HCS9VJE1 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Family of 16-bit CAN-enabled CompactRISC Microcontrollers |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。