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9.3.8
Data Memory Erase Time Reload Register
(DMERASE)
The DMERASE register is a byte-wide read/write register
that controls the erase pulse width. This value is loaded into
the upper 8 bits of the flash timing counter, and at the same
time, 11
2
is loaded into the lower 2 bits. Before you write to
the data memory for the first time, you should program the
DMERASE register with the proper prescaler value, an 8-bit
value called FTER. The flash timing counter generates a
erase pulse width of 4¥(FTER + 1) prescaler output clocks.
The default value provides a delay time of 1ms when the
prescaler output clock is 200kHz. Do not modify this register
while program/erase operation is in progress.
Upon reset, this register resets to 31
16
when the flash mem-
ory on the chip is in idle state.
For mass erase, this value should be changed to C7
16
when
the flash EEPROM data memory goes to idle mode.
9.3.9
Data Memory End Time Reload Register
(DMEND)
The DMEND register is a byte-wide read/write register that
controls the delay time after a program/erase operation. This
value is loaded into the lower 8 bits of the flash timing
counter, and at the same time, 00
2
is loaded into the upper 2
bits. Before you write to the data memory for the first time,
you should program the DMEND register with the proper
prescaler value, an 8-bit value called FTEND. The flash tim-
ing counter generates a delay of (FTEND + 1) prescaler out-
put clocks. The default value provides a delay time of 5ms
when the prescaler output clock is 200kHz. Do not modify
this register while program/erase operation is in progress.
Upon reset, this register resets to 00
16
when the flash mem-
ory on the chip is in idle state.
For mass erase, this value should be changed to 13
16
.
9.3.10
Data Memory Prescaler Count Register
(DMPCNT)
The DMPCNT register is a byte-wide read-only register that
returns the value of the data memory prescaler counter.
FPCNT is the flash timing prescaler present count value.
9.3.11
The DMCNT register is a word-wide read-only register that
returns the data memory timing counter value. The reserved
bits return 000000
2
.
FTCNT[0:9] is the flash timer present count value.
Data Memory Timer Count Register (DMCNT)
9.3.12
The DMKEY register is a byte-wide, read/write register that
provides a way to “l(fā)ock” the data contained in the EEPROM
data memory. Upon reset, the register is automatically set to
C9 hex, which is the key value. Writing to the EEPROM data
memory is allowed as long as the DMKEY register contains
this value. When the register contains any value other than
C9 hex, writing the EEPROM data memory is disallowed.
To “l(fā)ock” the current data stored in the data memory, write an-
other value (such as 00 hex) to the DMKEY register. To “un-
lock” the data memory, write the value C9 hex to the DMKEY
register.
Data Memory Write Key Register (DMKEY)
Note:
Operation of this register is different in from the
PGMKEY register used with the program memory. It is not
necessary to write the key value to DMKEY every time you
write to the data memory.
9.4
The In-System Program memory is part of the flash memory
array that contains the flash EEPROM data memory. It is not
possible to access the ISP memory while programming the
flash EEPROM data memory or access the flash EEPROM
data memory while programming the ISP memory. The 1.5K
bytes of ISP memory resides in the address range of E000-
E5FF and is used for storing the boot ROM. The ROM con-
tains the code that performs in-system programming, and is
programmed at the factory. In ISP mode, code execution
starts at address E000.
The ISP program memory and flash EEPROM data memory
share the same memory array, which makes it impossible to
access one type of memory while the other is being pro-
grammed.
The ISP memory has the following features:
— 1.5K bytes flash EEPROM program memory
— Page size of 4 words, divided into two rows of 2 words
each
— Odd and even bytes within a page can be erased sep-
arately
— 30ms programming pulse width per word
— Page mode erase with 1ms pulse, mass erase with
4ms pulse
— All erased memory bits read 1
— Fast read access time
— Requires valid key for program and erase to proceed
— Provide memory protection and security features for
flash EEPROM program memory
— Security features may limit accesses to ISP memory
— Disable memory when address is out of range to pre-
vent accessing data memory
— Mass erase only allowed in test modes
— Provide busy status during programming and erase
— Read/write accesses disabled during programming/
erase
— Programming high voltage and timing generated on-
chip
ISP MEMORY
9.4.1
The ISP flash EEPROM program memory read accesses
can operate without wait cycles with a CPU clock rate of up
to 20MHz in the normal mode. At higher clock rates, read ac-
cesses can operate with one wait state.
The programmed number of wait cycles used (either zero or
one) is controlled by BIU Configuration (BCFG) register and
the Static Zone 1 Configuration (SZCFG1) register. These
registers are described in Section 8.0.
Reading
9.4.2
All program and erase operations must be preceded by writ-
ing the proper key to the program memory key register ISP-
KEY. The programming code can be in-system RAM, but
cannot be from ISP flash EEPROM program memory or flash
EEPROM data memory as accesses within these ranges are
User-Coded Programming Routines