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15.0
Multi-Function Timer
The Multi-Function Timer (MFT16) module contains two in-
dependent timer/counter units called MFT1 and MFT2, each
containing a pair of 16-bit timer/counters. Each timer/counter
unit offers a choice of clock sources for operation and can be
configured to operate in any of the following modes:
Processor-Independent Pulse Width Modulation (PWM)
mode, which generates pulses of a specified width and
duty cycle, and which also provides a general-purpose
timer/counter
Dual Input Capture mode, which measures the elapsed
time between occurrences of external events, and which
also provides a general-purpose timer/counter
Dual Independent Timer mode, which generates system
timing signals or counts occurrences of external events
Single Input Capture and Single Timer mode, which pro-
vides one external event counter and one system timer
The two timer units, MFT1 and MFT2, are identical in opera-
tion and separately programmable. Each timer unit uses two
I/O pins, called T1A and T1B (for Timer MFT1) or T2A and
T2B (for Timer MFT2). The timer I/O pins are alternate func-
tions of the Port F I/O pins.
In the description of the timers, the lower-case letter “n” rep-
resents the timer number, either 1 or 2. For example, “TnA”
means I/O pin T1A or T2A.
15.1
Figure 11 is a block diagram showing the internal structure of
each timer. There are two main functional blocks: a Timer/
Counter and Action block and a Clock Source block. The
Timer/Counter and Action block contains two separate timer/
counter units, called Timer/Counter I and Timer/Counter II (a
total of four timer/counter unit in both MFT1 and MFT2).
TIMER STRUCTURE
15.1.1
The Timer/Counter block contains the following functional
blocks:
— two 16-bit counters, Timer/Counter I (TnCNT1) and
Timer/Counter II (TnCNT2)
— two 16-bit reload/capture registers, TnCRA and
TnCRB
— control logic necessary to configure the timer to oper-
ate in any of the four operating modes
— interrupt control and I/O control logic
In a power-saving mode that uses the low-frequency (32.768
kHz) clock as the system clock, the synchronization circuit
requires that the slow clock operate at no more than one-
fourth the speed of the 32.768 kHz system clock.
Timer/Counter Block
15.1.2
The Clock Source block generates the signals used to clock
the two timer/counter registers. The internal structure of the
Clock Source block is shown in Figure 12.
Clock Source Block
Counter Clock Source Select
There are two clock source selectors that allow the software
to independently select the clock source for each of the two
16-bit counters from any one of the following sources:
— no clock (which stops the counter)
— prescaled system clock
— external event count based on TnB
— pulse accumulate mode based on TnB
— slow clock (derived from the low-frequency oscillator or
divided from the high-speed oscillator)
Prescaler
The 5-bit clock prescaler allows the software to run the timer
with a prescaled clock signal. The prescaler consists of a 5-
bit read/write prescaler register (TnPRSC) and a 5-bit down
counter. The system clock is divided by the value contained
in the prescaler register plus 1. Thus, the timer clock period
can be set to any value from 1 to 32 divisions of the system
clock period. The prescaler register and down counter are
both cleared upon reset.
Figure 11.
Multi-Function Timer Block Diagram
Reload/Capture
A
Timer/Counter
1
Reload/Capture
B
Timer/Counter
2
Timer/Counter
Clock Source
Action
System
Clock
TnB
T
Mode Select + Control
PWM/Capture/Counter
TnA
External Event
Interrupt A
Interrupt B
C