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CXD1198AQ
(5)
XCS (Chip Select : negative logic input)
Chip select negative logic input signal for the CPU to read/write data with the register in this IC and the
host interface registers of the CXD1186BQ.
(6)
INT (CPU Interrupt : output)
Interrupt request signal to CPU
(7)
INTP (CPU Interrupt Polarity : input)
Selects the polarity of the INT signal; set to low when the INT signal turns to Low active and high when it
turns to High active.
1-6. Clock Signals (3 pins)
(1)
XTL1 (X’tal1 : input)
(2)
XTL2 (X’tal2 : output)
Inserts a crystal oscillator with a 24 MHZ oscillation frequency between the XTL1 and XTL2 pins.
Alternatively, inputs a 24 MHZ clock signal to the XTL1 pin.
(3)
HCLK (Half Clock : output)
Half frequency divided clock of XTL2.
1-7. Reset Signals (5 pins)
(1)
XRST (Reset : negative logic input)
Power on reset negative logic input signal
(2)
XSRS (SCSI Bus Reset : negative logic input)
SCSI bus reset negative logic input signal
(3)
XCRS (CPU Reset : negative logic output)
Reset negative logic output signal to the CPU; it is low in either of the cases below.
1) XRST = Low
2) XSRS = low
(4)
XHRS (SCSI Reset : negative logic output)
Reset negative logic output signal to the SCSI LSI (CXD1185); it is low in any of the cases below.
1) XRST = Low
2) XSRS = low
3) SCSI reset bit (Bit 2) of reset control register = high
(5)
XDRS (Drive Reset : negative logic output)
Reset negative logic output signal to drive block; it is low either of the cases below.
1) XRST = low
2) Drive reset bit (Bit 1) of reset control register = high