參數(shù)資料
型號(hào)： CXD1198AQ
廠商： Sony Corporation
英文描述： CD-ROM Subcode Decoder
中文描述： 光盤(pán)子碼解碼器
文件頁(yè)數(shù)： 40/51頁(yè)
文件大?。?/td> 426K
代理商： CXD1198AQ
—40—
CXD1198AQ
3-6. Host DMA Channel
(1)
Execution of DMA cycle
DMA transfer of the host DMA channel is requested when the HDRQ signal becomes activated, and the
DMA cycle is executed. For further details, refer to chapter 4.
(2)
Procedure for controlling IC from CPU
Described below is the procedure for controlling this IC when DMA transfer of the host DMA channel is
executed.
Write the number of bytes transferred into the Host DMA Transfer Counter.
Write the head address of the buffer memory, to which the data is transferred by DMA, into the
Host DMA Address Counter.
Write “1” into Bit 0 (host DMA enable) of DMA Control Register-2 and “0” or “1” into Bit 1 (host
DMA source) depending on the transfer direction. (When these are written, the DMA cycle
execution commences.)
When the DMA transfer of the number of bytes written into the Host DMA transfer counter is
completed, Bit 3 (host DMA complete) of the Interrupt Status Register is set to “1”. Also, the Host
DMA Transfer Register is zero, and the Host DMA address counter holds the value of the address
following the buffer memory address which was last transferred by DMA.
3-7. CPU DMA Channel
(1)
Execution of DMA cycle
DMA transfer of the CPU DMA channel is requested by read/write with the CPU DMA Data Register, and
the DMA cycle is executed.
(2)
Procedure for controlling IC from CPU
Described below is the procedure for controlling this IC when DMA transfer of the CPU DMA channel is
executed.
Write the head address of the buffer memory, to which the data is transferred by DMA, into the
CPU DMA Address Counter.
Write “1” into Bit 3 (CPU DMA enable) of DMA Control Register-2 and “0” or “1” into Bit 4 (CPU
DMA source) depending on the direction of transfer. (When these are written, the DMA cycle
execution commences.)
In reading data from the buffer memory, Bit 1 (CPU buffer read ready) of the BMM Status Register
is set to “1” when the data read from the buffer memory is written into the CPU DMA Data
Register. Therefore, first check this status and then read the data from the CPU DMA Data
Register. When the data is read from the CPU DMA Data Register, Bit 1 returns to “0" and the
CPU DMA Address Register is incremented. When the next data is written into the CPU DMA
Data Register from the buffer memory, the Bit is again set to “1”. Check this status and then read
the next data from the CPU DMA Data Register.
In writing data into the buffer memory, first check that Bit 2 (CPU buffer write ready) of the BMM
Status Register is “1” and then write the data into the CPU DMA Data Register. Bit 2 (CPU buffer
write ready) is set to “0” when the data is written in the CPU DMA Data Register but when this
data is written into the buffer memory, it returns to “1” and the CPU DMA Address Register is
incremented. Check that Bit 2 is set to “1” again and then write the next data into the CPU DMA
Data Register.
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參數(shù)描述
CXD1199AQ 制造商:SONY 制造商全稱(chēng):Sony Corporation 功能描述:CD-ROM DECODER
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CXD12-15 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Analog IC
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