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CXD1198AQ
(9)
Drive DMA Address Counter Lower (08H)
(10) Drive DMA Address Counter Middle (09H)
(11) Drive DMA Address Counter Upper (0AH)
These are 20-bit registers for setting the address from which to start the DMA transfer with the
CXD1186BQ. Their values are incremented each time 1 byte has been transferred by DMA.
(12) Drive DMA Transfer Counter Lower (0BH)
(13) Drive DMA Transfer Counter Upper (0CH)
These are 12-bit registers for setting the number of bytes to be transferred by DMA with the CXD1186BQ.
Their values are decremented each time 1 byte has been transferred by DMA.
(14) Error Pointer DMA Address Counter Lower (0DH)
(15) Error Pointer DMA Address Counter Middle (0EH)
(16) Error Pointer DMA Address Counter Upper (0FH)
These are 20-bit registers for setting the address from which to start writing error pointers from the
CXD1186BQ when Bit 3 (pointer transfer mode) of the DMA Control Register is “0”. Their values are
incremented each time 8 bits (1 byte) have been transferred by DMA.
(17) Subcode P-W DMA Address Counter Lower (10H)
(18) Subcode P-W DMA Address Counter Middle (11H)
(19) Subcode P-W DMA Address Counter Upper (12H)
These are 20-bit registers for setting the address from which to start writing the channel P-W subcodes
from the CXD2500. Their values are incremented each time 1 byte (1 symbol) has been transferred by
DMA.
(20) Host DMA Address Counter Lower (13H)
(21) Host DMA Address Counter Middle (14H)
(22) Host DMA Address Counter Upper (15H)
These are 20-bit registers for setting the address from which to start the data transfer by DMA with the
host. Their values are incremented each time 1 byte has been transferred by DMA.
(23) Host DMA Transfer Counter Lower (16H)
(24) Host DMA Transfer Counter Upper (17H)
These are 16-bit registers for setting the number of bytes transferred by DMA with the host. Their values
are decremented each time 1 byte has been transferred by DMA.