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CXD1198AQ
(25) CPU DMA Address Counter Lower (18H)
(26) CPU DMA Address Counter Middle (19H)
(27) CPU DMA Address Counter Upper (1AH)
These are 20-bit registers for setting the address from which to start the data transfer by DMA with the
CPU. Their values are incremented each time 1 byte has been transferred by DMA.
(28) Configuration Register (1BH)
Bit 0 : CDL 3
×
Series
This bit is set to “1” when connected to the CDL30 or 35 series LSI.
Bit 1 : Packet Mode
When this bit is “0”, transfers the decoded data in 4 packs to the DRAM for each subcode sync;
when it is “1”, transfers the decoded data in 4 packs starting from the pack prior to the fifth pack
to the DRAM for each subcode sync.
Bit 2 : Buffer Memory Size 1
Bit 3 : Buffer Memory Size 2
Select the buffer memory size : 64 kB with (Bit 3, Bit 2) = (0, 0), 256 kB with (0, 1) and 1 MB
with (1, x).
Bit 4 : Error Pointer Write Data
Sets the error pointer (DDBP) value when data is transferred by DMA from the buffer memory
to the CXD1186BQ.
Bit 5 : HCLK Disable Mode
The HCLK output remains low when this bit is “1”. When “0”, a clock signal with half the
frequency of XTL2 is output from the HCLK output.
Bit 6 : Reserved
Bit 7 : Reserved
(29) Drive Command Register (20H)
The command register for the host interface of the CXD1186BQ is mapped in the register address space
of this IC.
(30) Drive Parameter Register (21H)
The parameter register for the host interface of the CXD1186BQ is mapped in the register address space
of this IC.
(31) Drive Write Data Register (22H)
The write data register for the host interface of the CXD1186BQ is mapped in the register address space
of this IC.
(32) Drive Control Register (23H)
The control register for the host interface of the CXD1186BQ is mapped in the register address space of
this IC.