參數(shù)資料
型號(hào)： CXD1198AQ
廠商： Sony Corporation
英文描述： CD-ROM Subcode Decoder
中文描述： 光盤子碼解碼器
文件頁(yè)數(shù)： 44/51頁(yè)
文件大小： 426K
代理商： CXD1198AQ
—44—
CXD1198AQ
(2)
Host and CPU control procedure
Fig. 4-2 shows and example of the host and CPU control procedure. In this example, the host gets to
know the interrupt status by polling the Status register.
(3)
Data transfer between host and buffer memory
This IC contains 2
×
8-bit FIFO registers (WRDATA, RDDATA), and data can be transferred at 4 MB/s
maximum.
(3-1)Data transfer in DMA mode
Data is transferred between the host and this IC by means of handshaking using the HDRQ/XSAC and
XHAC/SDRQ pins.
The HDRQ/XSAC pin outputs the HDRQ signal requesting data transfer from the IC to the host and the
XHAC/SDRQ becomes the corresponding acknowledge signal XHAC.
Data transfer from host to buffer memory (host DMA source bit = “1”)
When the host DMA enable bit is “1” while FIFO is not full and the XHAC pin is high, this IC sets
the HDRQ pin high. When the acknowledge signal returns from the host, the HDRQ pin is set
low. Data from the host is retrieved in this IC at the XHAC pin rising. The data retrieved is written
in sequence into the addresses of the buffer memory selected by the Host Address Counter
Register.
Data transfer from buffer memory to host (host DMA source bit = “0”)
When the host DMA enable bit is “1”, the data in the address of the buffer memory selected by the
Host Address Counter Register is retrieved in this IC. When the buffer memory data is retrieved,
this IC sets the HDRQ pin high if the XHAC pin is “1”. When the acknowledge signal returns from
the host, the HDRQ pin is set low. While this pin is low, this IC outputs the data retrieved from the
buffer memory to host bus HDB0 to 7.
(3-2)Data transfer in the I/O mode
The host can transfer data with the buffer memory by writing or reading the WRDATA or RDDATA
registers. In this case, the control of this IC by the CPU is not different from that in the DMA mode. Fig.
4-3 shows the host control flow when data is transferred between the host and buffer memory in the I/O
mode.
(3-3)Completion of data transfer
There are two following methods to complete data transfer.
By using the Host Transfer Counter. (This is the usual method.)
By setting the host DMA enable bit to “0”.
When using the Host Transfer Counter
When transferring data using the Host Transfer Counter, the CPU should perform the following
operations prior to the data transfer.
· Write the number of bytes for data transferred into the Host Transfer Counter.
· Write the data transfer direction (host DMA source) and “1” into the host DMA enable bit.
When these are written, data transfer commences.
The Host Transfer Counter is decremented each time data is written into FIFO. When its value is
reduced to zero, further data is not written into FIFO. When all the FIFO data is read out, the host
DMA complete status (Interrupt Status Register Bit 2) sets on.
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