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參數(shù)資料
| 型號： | CXD1198AQ |
| 廠商： | Sony Corporation |
| 英文描述： | CD-ROM Subcode Decoder |
| 中文描述： | 光盤子碼解碼器 |
| 文件頁數(shù)： | 42/51頁 |
| 文件大?。?/td> | 426K |
| 代理商： | CXD1198AQ |
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CXD1198AQ
Bit 6 : CLRPRM (clear parameter)
The Parameter register can be cleared by writing “1” into this bit. This bit automatically returns to
“0” after the Parameter register is cleared. So, there is no need to write “0” again.
Bit 7 : CHPRST (chip reset)
This IC is internally initialized by writing “1” into this bit. This bit automatically returns to “0” upon
completion of the initializing. So, there is no need to write “0” again. An interrupt request can be
generated to the CPU by writing “1” into this bit.
Read registers
Status register (00H)
This register is for the host to read the statuses in this IC.
Bit 0 to 2 : INTSTS #1 to 3 (interrupt status #1 to 3)
The values of these bits correspond to that of Bits 0 to 2 in the CPU’s Host Interface Control
Register respectively. When each bit is “1”, an interrupt request is generated to the host provided
that the corresponding interrupt of the bit is enabled.
Bit 3 to 5 : ENINTST #1 to 3 (enable interrupt status #1 to 3)
The values of these bits correspond to that of Bits 3 to 5 in the control register.
Bit 6 : Data request status
This bit has the same value as the HDRQ pin, and it indicates that the IC has requested the host
for buffer memory data transfer. When transferring data in the I/O mode, access the WRDATA or
RDDATA registers after the host has checked that this bit is “1”.
Bit 7 : Busy status
This bit is set to “1” by the host writing a command in the Command register. It is set to “0” by the
CPU writing “1” into the clear busy bit of the Host Interface Control Register.
Result register (01H)
The host reads the results after the command execution from this register. This is a 10-byte FIFO
register.
RDDATA (read data) register (02H)
This register is for the host to read the data from the buffer memory. Data can be read in the I/O
mode or DMA mode.
FIFO status register (03H)
This register is for the host to read the status of the parameter register or the host result register.
Bit 0 : Parameter write ready
When this bit is “1”, it indicates that the Parameter register is not full and the host can write
parameter data.
Bit 1 : Parameter empty
When this bit is “1”, it indicates that the Parameter register is empty.
Bit 2 : Result read ready
When this bit is “1”, it indicates that the Host Result register is not empty and the host can read
result data.
Bit 3 : Result full
When this it is “1”, it indicates that the Host Result register is full.
Bit 4 to 7 : Reserved
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| CXD1199AQ | CD-ROM DECODER |
| CXD1257AR | CCD Camera Timing Generator |
| CXD1267AN | CCD Vertical Clock Driver |
| CXD1806 | CD-ROM DECODER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD1199AQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD-ROM DECODER |
| CXD12-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CXD12-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CXD1217 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Synchronizing Signal Generator for Video Camera |
| CXD1217M | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Synchronizing Signal Generator for Video Camera |
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