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參數(shù)資料
| 型號： | CXD1198AQ |
| 廠商： | Sony Corporation |
| 英文描述： | CD-ROM Subcode Decoder |
| 中文描述： | 光盤子碼解碼器 |
| 文件頁數(shù)： | 41/51頁 |
| 文件大小： | 426K |
| 代理商： | CXD1198AQ |
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CXD1198AQ
4. Host Interfaces
4-1. Overview
The CXD1198AQ can be connected with the Intel 80-series host bus or SCSI control LSI (CXD1185, etc.)
as the host interface. The selection can be made by the HMDS pin as follows.
When connecting with the Intel 80-series host bus, input a low logic level to the HMDS pin or leave it
open; when connecting with the SCSI control LSI, input a high logic level to the HMDS pin.
Except for the fact that the XTC pin is not supported, the host interface specifications of this IC are the
same as those for the CXD1186BQ.
4-2. When connecting with the Intel 80-series host bus
When connecting this IC with the Intel 80-series host bus, input a low logic level to the HMDS pin or leave
it open. Fig. 4-1 shows and example of the connection.
(1)
Commands/statuses transfer between host and CPU
The host can access each of the four write and read registers using the HA0, HA1, XHCS, XHRD and
XHWR pins. The DMA transfer mode is also supported by the WRDATA and RDDATA registers and,
regardless of the HA0, HA1 and XHCS pin values, the registers are selected by the XHAC, XHRD and
XHWR pins, and DMA transfer is conducted between the host and buffer memory. The Parameter
Register and Result Register are 10-byte FIFO registers.
Inputting a low logic level to both the XHAC and XHCS pins is prohibited at the same time.
Write registers
Command register (00H)
The host writes commands into this register. When it does this, and interrupt request is applied
from this IC to the CPU. Bit assignment and function attribution is performed by the drive control
program.
Parameter register (01H)
The host writes into this register command parameters required for the CPU to execute the
commands. This is a 10-byte FIFO register.
WRDATA (write data) register (02H)
This register is for writing data into the buffer memory from the host. Data can be written in either
the I/O mode or DMA mode.
Control register (03H)
This register is for the direct control of the hardware in this IC by the host.
Bit 0 to 2 : INTCLR#1 to 3 (interrupt clear #1 to 3)
By writing “1” into any of these bits, the corresponding interrupt status is cleared. These bits
automatically return to “0” after the interrupt status interrupt is cleared. So, there is no need to
write “0” again.
Bit 3 to 5 : ENINT #1 to 3 (enable interrupt #1 to 3)
By writing “1” into any of these bits, the corresponding interrupt status is enabled. The host can
also read the values of these bits from the Status register.
Writing “1" into a bit is prohibited when its corresponding interrupt status is high. Therefore,
before writing “1” into any of these bits, the host must read the Status register and check its
interrupt status.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD1199AQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD-ROM DECODER |
| CXD12-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CXD12-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CXD1217 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Synchronizing Signal Generator for Video Camera |
| CXD1217M | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Synchronizing Signal Generator for Video Camera |
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