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參數(shù)資料
| 型號： | CXD1198AQ |
| 廠商： | Sony Corporation |
| 英文描述： | CD-ROM Subcode Decoder |
| 中文描述： | 光盤子碼解碼器 |
| 文件頁數(shù)： | 25/51頁 |
| 文件大?。?/td> | 426K |
| 代理商： | CXD1198AQ |
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CXD1198AQ
(8)
Host Interface Status Register (07H)
This register is used to know the status of the host interface hardware when the HMDS pin is low. It has
the same specifications as the Host Interface Control Register of the CXD1186BQ.
Bit 0 : Host Interrupt Status #1
This bit turns to “1” when the CPU writes “1” into host interrupt #1 (Host Interface Control
Register Bit 0). It is set to “0” when the host writes “1” into CLRINT #1 (Control Register Bit 0).
This bit is used to monitor the interrupt status to the host.
Bit 1 : Host Interrupt Status #2
This bit turns to “1” when the CPU writes “1” into host interrupt #2 (Host Interface Control
Register Bit 1). It is set to “0” when the host writes “1” into CLRINT #2 (Control Register Bit 1).
This bit is used to monitor the interrupts status to the host.
Bit 2 : Host Interrupt Status #3
This bit turns to “1” when the CPU writes “1” into host interrupt #3 (Host Interface Control
Register Bit 2). It is set to “0” when the host writes “1” into CLRINT #3 (Control Register Bit 2).
This bit is used to monitor the interrupts status to the host.
Bit 3:
Parameter Read Ready
When this bit is “1”, it indicates that the Parameter Register of the host is not empty and
parameter data can be read from the CPU. When “0”, the Parameter Register is empty.
Bit 4:
Parameter Full
When this bit is “1”, it indicates that the Parameter Register of the host is full.
Bit 5:
Result Write Ready
When this bit is “1”, it indicates that the Host Result Register is not full and result data can be
written from the CPU. When “0”, the Host Result Register is full and the CPU cannot write the
result data into the register.
Bit 6:
Result Empty
When this bit is “1”, it indicates that the Host Result Register is empty.
Bit 7:
Busy Status
This bit has the same value as Bit 7 of the Host Status Register. It is set to “1” when the host
writes a command in the Command Register. It is set to “0” when the CPU writes “1” into the
Clear Busy Bit of the Host Interface Control Register.
(9)
Drive DMA Address Counter Lower (08H)
(10) Drive DMA Address Counter Middle (09H)
(11) Drive DMA Address Counter Upper (0AH)
Indicate the Drive DMA Address Counter values.
(12) Drive DMA Transfer Counter Lower (0BH)
(13) Drive DMA Transfer Counter Upper (0CH)
Indicate the Drive DMA Transfer Counter values.
(14) Error Pointer DMA Address Counter Lower (0DH)
(15) Error Pointer DMA Address Counter Middle (0EH)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXD1199AQ | CD-ROM DECODER |
| CXD1257AR | CCD Camera Timing Generator |
| CXD1267AN | CCD Vertical Clock Driver |
| CXD1806 | CD-ROM DECODER |
| CXD1806AQ | CD-ROM DECODER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXD1199AQ | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:CD-ROM DECODER |
| CXD12-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CXD12-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CXD1217 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Synchronizing Signal Generator for Video Camera |
| CXD1217M | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:Synchronizing Signal Generator for Video Camera |
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