參數(shù)資料
型號： CY39200V208-83NTXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 15 ns, PQFP208
封裝： 28 X 28 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, EQFP-208
文件頁數(shù)： 12/86頁
文件大?。?/td> 2802K
代理商： CY39200V208-83NTXC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *I
Page 2 of 86
Notes:
3.
Speed bins shown here are for commercial operating range. Please refer to Delta39K ordering information on industrial-range speed bins on page 37.
4.
Self-boot solution integrates the boot PROM (flash memory) with Delta39K die inside the same package. This flash memory can endure at least 10,000
programming/erase cycles and can retain data for at least 100 years.
Delta39K Speed Bins[3]
Device
VCC
233
200
181
125
83
39K30
3.3/2.5V
X
39K50
3.3/2.5V
X
39K100
3.3/2.5V
X
39K200
3.3/2.5V
X
Device Package Offering and I/O Count Including Dedicated Clock and Control Inputs
Device
208 EQFP
28 × 28 mm
0.5-mm pitch
256 FBGA
17 × 17 mm
1.0-mm pitch
484-FBGA
23 × 23 mm
1.0-mm pitch
Self-Boot Solution[4]
256-FBGA
17 × 17 mm
1.0-mm pitch
388-BGA
35 × 35 mm
1.27-mm pitch
484-FBGA
23 × 23 mm
1.0-mm pitch
676-FBGA
27 × 27 mm
1.0-mm pitch
39K30
136
174
39K50
136
180
218
39K100
136
180
302
294
302
39K200
136
368
294
428
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相關代理商/技術參數(shù)
參數(shù)描述
CY39200V256-125MBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V256-125MGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V256-181BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V256-181MBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200V256-181MGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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