參數(shù)資料
型號： CY39200V208-83NTXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： LOADABLE PLD, 15 ns, PQFP208
封裝： 28 X 28 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, EQFP-208
文件頁數(shù)： 39/86頁
文件大小： 2802K
代理商： CY39200V208-83NTXC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *I
Page 44 of 86
Pin Tables
Package Diagrams (continued)
676-Ball FBGA (27 x 27 x 1.6 mm) BB676/MB676
51-85125-*B
Table 8. Pin Definition Table
Pin Name
Function
Description
GCLK0-3
Input
Global Clock signals 0 through 3
GCTL0-3
Input
Global Control signals 0 through 3
GND
Ground
IO/VREF0
Input/Output
Dual function pin: IO or Reference Voltage for Bank 0
IO/VREF1
Input/Output
Dual function pin: IO or Reference Voltage for Bank 1
IO/VREF2
Input/Output
Dual function pin: IO or Reference Voltage for Bank 2
IO/VREF3
Input/Output
Dual function pin: IO or Reference Voltage for Bank 3
IO/VREF4
Input/Output
Dual function pin: IO or Reference Voltage for Bank 4
IO/VREF5
Input/Output
Dual function pin: IO or Reference Voltage for Bank 5
IO/VREF6
Input/Output
Dual function pin: IO or Reference Voltage for Bank 6
IO/VREF7
Input/Output
Dual function pin: IO or Reference Voltage for Bank 7
IO
Input/Output
Input or Output pin
IO6/Lock
Input/Output
Dual function pin: IO in Bank 6 or PLL lock output signal
MSEL
Input
Mode Select Pin (see Table 9)
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