參數(shù)資料
型號： CY3930V484-125BBC
廠商： Cypress Semiconductor Corp.
英文描述： CPLDs at FPGA Densities
中文描述： CPLD器件在FPGA的密度
文件頁數(shù)： 11/86頁
文件大?。?/td> 1212K
代理商： CY3930V484-125BBC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 19 of 86
tCKIN
Delay from the clock pin to the input of the clock driver
tIOREGPIN
Delay from the I/O pin to the input of the I/O register
PLL Parameters
tMCCJ
Maximum cycle to cycle jitter time
tDWSA
PLL zero phase delay with clock tree deskewed
tDWOSA
PLL zero phase delay without clock tree deskewed
tLOCK
Lock time for the PLL
tINDUTY
Input duty cycle
fPLLI
Input frequency of the PLL
fPLLO
Output frequency of the PLL
fPLLVCO
PLL VCO frequency of operation
PSAPLLI
Percentage modulation allowed (spread awareness) on the PLL input clock
fMPLLI
Frequency of modulation allowed on PLL input clock. This specifies how fast the fPLLI sweeps between fPLLI*
(1–PSAPLLI/100) and fPLLI* (1+ PSAPLLI/100)
JTAG Parameters
tJCKH
TCLK HIGH time
tJCKL
TCLK LOW time
tJCP
TCLK clock period
tJSU
JTAG port set-up time (TDI/TMS inputs)
tJH
JTAG port hold time (TDI/TMS inputs)
tJCO
JTAG port clock to output time (TDO)
tJXZ
JTAG port valid output to high impedance (TDO)
tJZX
JTAG port high impedance to valid output (TDO)
Switching Characteristics — Parameter Descriptions Over the Operating Range[13] (continued)
Parameter
Description
Cluster Memory Timing Parameter Descriptions Over the Operating Range
Parameter
Description
Asynchronous Mode Parameters
tCLMAA
Cluster memory access time. Delay from address change to Read data out
tCLMPWE
Write Enable pulse width
tCLMSA
Address set-up to the beginning of Write Enable with both signals from the same I/O block
tCLMHA
Address hold after the end of Write Enable with both signals from the same I/O block
tCLMSD
Data set-up to the end of Write Enable
tCLMHD
Data hold after the end of Write Enable
Synchronous Mode Parameters
tCLMCYC1
Clock cycle time for flow through Read and Write operations (from macrocell register through cluster memory
back to a macrocell register in the same cluster)
tCLMCYC2
Clock cycle time for pipelined Read and Write operations (from cluster memory input register through the
memory to cluster memory output register)
tCLMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
tCLMH
Address, data, and WE hold time of pin inputs, relative to a global clock
tCLMDV1
Global clock to data valid on output pins for flow through data
tCLMDV2
Global clock to data valid on output pins for pipelined data
tCLMMACS1
Cluster memory input clock to macrocell clock in the same cluster
tCLMMACS2
Cluster memory output clock to macrocell clock in the same cluster
tMACCLMS1
Macrocell clock to cluster memory input clock in the same cluster
相關PDF資料
PDF描述
CY3950V484-125BBC CPLDs at FPGA Densities
CY54FCT540CTDMB FCT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP20
CY54FCT543CTDMB FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDIP24
CY54FCT543ATDMB FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDIP24
CY54FCT543ATLMB FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CQCC28
相關代理商/技術參數(shù)
參數(shù)描述
CY3930V484-125BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3930V484-125BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3930V484-125BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3930V484-125MBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3930V484-125MBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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