參數(shù)資料
型號(hào): CY3930V484-125BBC
廠(chǎng)商: Cypress Semiconductor Corp.
英文描述: CPLDs at FPGA Densities
中文描述: CPLD器件在FPGA的密度
文件頁(yè)數(shù): 14/86頁(yè)
文件大?。?/td> 1212K
代理商: CY3930V484-125BBC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 21 of 86
Internal Parameters
tCHMCHAA
Asynchronous channel memory access time from input of channel memory to output of channel memory
Channel Memory Timing Parameter Descriptions Over the Operating Range (continued)
Parameter
Description
Switching Characteristics — Parameter Values Over the Operating Range
Parameter
233
200
181
125
83
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Combinatorial Mode Parameters
tPD
7.2
7.5
8.5
10
15
ns
tEA
4.5
5.0
5.6
9.0
10
ns
tER
4.5
5.0
5.3
9.0
10
ns
tPRR
6.0
8.0
10
ns
tPRO
9.5
10
10.5
13
15
ns
tPRW
3.3
3.6
4.0
6.0
7.0
ns
Synchronous Clocking Parameters
tMCS
2.7
3.0
3.5
5.0
6.7
ns
tMCH
00
0
ns
tMCCO
5.8
6.0
7.0
10
12
ns
tIOS
1.0
1.2
2.0
2.5
ns
tIOH
0.9
1.0
1.2
2.0
2.5
ns
tIOCO
3.8
4.0
4.5
7.0
8.0
ns
tSCS
3.4
3.5
3.6
6.4
9.6
ns
tSCS2
4.3
4.5
5.5
8.0
12
ns
tICS
4.5
5.0
5.5
8.0
12
ns
tOCS
4.5
5.0
5.5
8.0
12
ns
tCHZ
3.5
3.8
6.0
7.0
ns
tCLZ
1.5
ns
fMAX
294
286
278
156
104
MHz
fMAX2
233
222
181
125
83
MHz
Product Term Clocking Parameters
tMCSPT
2.7
3.0
3.3
5.0
6.0
ns
tMCHPT
0.9
1.0
1.4
2.0
2.5
ns
tMCCOPT
7.5
8.0
8.8
11.0
15.0
ns
tSCS2PT
6.0
6.5
7.2
10.0
15.0
ns
Channel Interconnect Parameters
tCHSW
0.9
1.0
1.2
1.7
2.0
ns
tCL2CL
1.8
2.0
2.3
2.8
3.0
ns
Miscellaneous Parameters
tCPLD
2.8
3.0
3.3
4.0
5.0
ns
tMCCD
0.22
0.25
0.28
0.35
0.38
ns
PLL Parameters
tMCCJ
–150
150
–150
150
–150
150
–180
180
–200
200
ps
tDWSA
–1.35
–0.85
–1.35
–0.85
–1.35
–0.85
–2.0
–1.5
–2.9
–2.4
ns
tDWOSA
–150
150
–150
150
–150
150
–180
180
–200
200
ps
tLOCK
250
ms
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