參數(shù)資料
型號: CY3930V484-125BBC
廠商: Cypress Semiconductor Corp.
英文描述: CPLDs at FPGA Densities
中文描述: CPLD器件在FPGA的密度
文件頁數(shù): 79/86頁
文件大?。?/td> 1212K
代理商: CY3930V484-125BBC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 80 of 86
J16
IO/VREF6
J17
IO6
J18
GND
J19
TCLK
J20
IO5
J21
IO5
J22
IO5
J23
IO5
J24
NC
IO5
J25
NC
J26
NC
K1
NC
K2
NC
K3
NC
IO0
K4
IO0
K5
IO0
K6
IO0
K7
IO0
K8
IO0
K9
IO0
K10
IO7
K11
IO7
K12
IO7
K13[19]
IO7
K14[19]
IO6
K15
IO6
K16
IO6
IO6[20]
IO6
K17
TMS
K18
IO5
K19
IO5
K20
IO5
K21
IO5
K22
IO5
K23
IO5
K24
NC
IO5
K25
NC
K26
NC
L1
NC
L2
NC
L3
NC
IO/VREF0
L4
NC
VCCIO0
L5
IO/VREF0
L6
IO0
L7
VCC
Table 15. 676 FBGA Pin Table (continued)
Pin
CY39100
CY39165
CY39200
L8
VCCIO0
L9
IO/VREF0
L10
IO0
L11
IO7
L12
GCTL3
L13
GCLK3
L14
GCTL2
L15
GCLK2
L16
IO5
L17
IO5
L18
IO/VREF5
L19
VCCIO5
L20
VCCJTAG
L21
IO5
L22
IO/VREF5
L23
NC
VCCIO5
L24
NC
IO/VREF5
L25
NC
L26
NC
M1
NC
M2
NC
M3
NC
IO0
M4
IO0
M5
IO0
M6
IO0
M7
VCC
M8
VCCIO0
M9
IO/VREF0
M10
IO0
M11
GCTL0
M12
GND
M13
GND
M14
GND
M15
GND
M16
GCTL1
M17
IO5
M18
IO/VREF5
M19
VCCIO5
M20
VCC
M21
IO5
M22
IO5
M23
IO5
M24
NC
IO5
M25
NC
Table 15. 676 FBGA Pin Table (continued)
Pin
CY39100
CY39165
CY39200
相關PDF資料
PDF描述
CY3950V484-125BBC CPLDs at FPGA Densities
CY54FCT540CTDMB FCT SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP20
CY54FCT543CTDMB FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDIP24
CY54FCT543ATDMB FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDIP24
CY54FCT543ATLMB FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CQCC28
相關代理商/技術參數(shù)
參數(shù)描述
CY3930V484-125BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3930V484-125BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3930V484-125BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3930V484-125MBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY3930V484-125MBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities