參數(shù)資料
型號(hào)： CY3930V484-125BBC
廠商： Cypress Semiconductor Corp.
英文描述： CPLDs at FPGA Densities
中文描述： CPLD器件在FPGA的密度
文件頁(yè)數(shù)： 4/86頁(yè)
文件大小： 1212K
代理商： CY3930V484-125BBC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 12 of 86
Table 6 describes the valid phase shift options that can be
used with or without an external feedback.
Table 7 is an example of the effect of all the available divide
and phase shift options on a VCO output of 250 MHz. It also
shows the effect of division on the duty cycle of the resultant
clock. Note that the duty cycle is 50-50 when a VCO output is
divided by an even number. Also note that the phase shift
applies to the VCO output and not to the divided output.
For more details on the architecture and operation of this PLL
please refer to the application note entitled “Delta39K PLL and
Clock Tree”.
Table 4. Valid PLL Multiply and Divide Options—without External Feedback
Input Frequency
(GCLK[0])
fPLLI (MHz)
Valid Multiply Options
Valid Divide Options
Value
VCO Output
Frequency (MHz)
Value
Output Frequency (INTCLK[3:0])
fPLLO (MHz)
Off-chip Clock
Frequency
DC–12.5
N/A
DC–12.5
DC–6.25
100–133
1
100–133
1–6, 8, 16
6.25–133
3.125–66
50–133
2
100–266
1–6, 8, 16
6.25–266
3.125–133
33.3–88.7
3
100–266
1–6, 8, 16
6.25–266
3.1–266
25–66
4
100–266
1–6, 8, 16
6.25–266
3.125–133
20–53.2
5
100–266
1–6, 8, 16
6.25–266
3.1–133
16.6–44.3
6
100–266
1–6, 8, 16
6.25–266
3.1–133
12.5–33
8
100–266
1–6, 8, 16
6.25–266
3.125–133
12.5–16.625
16
200–266
1–6, 8, 16
6.25–266
3.125–133
Table 5. Valid PLL Multiply and Divide Options—With External Feedback
Input (GCLK) Frequency
fPLLI (MHz)
Valid Multiply Options
Valid Divide Options
Value
VCO Output
Frequency (MHz)
Value
Output (INTCLK) Frequency
fPLLO (MHz)
Off-chip Clock
Frequency
50–133
1
100–266
1
100–266
50–133
25–66.5
1
100–266
2
50–133
25–66.5
16.67–44.33
1
100–266
3
33.33–88.66
16.67–44.33
12.5–33.25
1
100–266
4
25–66.5
12.5–33.25
12.5–26.6
1
125–266
5
25–53.2
12.5–26.6
12.5–22.17
1
150–266
6
25–44.34
12.5–22.17
12.5–16.63
1
200–266
8
25–33.25
12.5–16.63
Table 6. Recommended PLL Phase Shift Options
Without External Feedback
With External Feedback
0°,45°, 90°, 135°, 180°, 225°, 270°, 315°
0°
Table 7. Timing of Clock Phases for all Divide Options for a VCO Output Frequency of 250 MHz
Divide
Factor
Period
(ns)
Duty Cycle%
0°
(ns)
45°
(ns)
90°
(ns)
135°
(ns)
180°
(ns)
225°
(ns)
270°
(ns)
315°
(ns)
1
4
40–60
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
2
8
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
3
12
33–67
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4
16
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
5
20
40–60
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
6
24
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
8
32
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
16
64
50
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
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CY3930V484-125BBI 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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CY3930V484-125MBC 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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