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PRELIMINARY
PSoC 5: CY8C53 Family Datasheet
Document Number: 001-55035 Rev. *G
Page 4 of 102
Figure 1-1 illustrates the major components of the CY8C53
family. They are:
ARM Cortex-M3 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast,
low-power UDBs. PSoC Creator provides a library of pre-built
and tested standard digital peripherals (UART, SPI, LIN, PRS,
CRC, timer, counter, PWM, AND, OR, and so on) that are
mapped to the UDB array. The designer can also easily create a
digital circuit using boolean primitives by means of graphical
design entry. Each UDB contains programmable array logic
(PAL)/programmable logic device (PLD) functionality, together
with a small state machine engine to support a wide variety of
peripherals.
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C53 family these blocks can include four 16-bit timer,
counter, and PWM blocks; I2C slave, master, and multimaster;
Full-Speed USB; and Full CAN 2.0b.
For more details on the peripherals see the
“Exampleinformation on UDBs, DSI, and other digital blocks, see the
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 0.1% error
over temperature and voltage. The configurable analog
subsystem includes:
Analog muxes
Comparators
Analog mixers
Voltage references
Analog-to-Digital Converters (ADC)
Digital-to-Analog Converters (DACs)
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals.
The CY8C53 family also offers a SAR ADC. Featuring 12-bit
conversions at up to 1 M samples per second, it also offers low
nonlinearity and offset errors and SNR better than 70 dB. It is
well suited for a variety of higher speed analog applications.
Two high speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
DAC outputs using the UDB array. This can be used to create a
pulse width modulated (PWM) DAC of up to 10 bits, at up to
48 kHz. The digital DACs in each UDB support PWM, PRS, or
delta-sigma algorithms with programmable widths.
In addition to the ADC and DACs, the analog subsystem
provides multiple:
Comparators
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
datasheet for more details.
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 80 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, flash
cache, and RAM. The NVIC provides low latency, nested
interrupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The flash cache also reduces system power consumption by
allowing less frequent flash access.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 256 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling boot loaders. The designer can enable
an error correcting code (ECC) for high reliability applications. A
powerful and flexible protection model secures the user's
sensitive information, allowing selective memory block locking
for read and write protection. Two KB of byte-writable EEPROM
is available on-chip to store application data. Additionally,
selected configuration options such as boot speed and pin drive
mode are stored in nonvolatile memory. This allows settings to
activate immediately after POR.