參數(shù)資料
型號： CY8C5386AXI-081
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 外設(shè)及接口
英文描述： MULTIFUNCTION PERIPHERAL, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLAINT, MS-026, TQFP-100
文件頁數(shù)： 67/102頁
文件大?。?/td> 2374K
代理商： CY8C5386AXI-081
PRELIMINARY
PSoC 5: CY8C53 Family Datasheet
Document Number: 001-55035 Rev. *G
Page 67 of 102
11.4.3 USBIO
For operation in USB mode, VDDD range condition is 3.15 V VDDD 3.45 V (USB regulator bypassed) or 4.35 V VDDD 5.25 V
(USB regulator in use). For operation in GPIO mode, the standard range for VDDD applies, see Device Level Specifications on page 60.
Table 11-12. USBIO DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Rusbi
USB D+ pull-up resistance
With idle bus
0.900
–
1.575
k
Rusba
USB D+ pull-up resistance
While receiving traffic
1.425
–
3.090
k
Vohusb
Static output high
15 k
±5% to Vss, internal pull-up
enabled
2.8
–
3.6
V
Volusb
Static output low
15 k
±5% to Vss, internal pull-up
enabled
–
0.3
V
Vohgpio
Output voltage high, GPIO mode
IOH = 4 mA, VDDD 3 V
2.4
–
V
Volgpio
Output voltage low, GPIO mode
IOL = 4 mA, VDDD 3 V
–
0.3
V
Vdi
Differential input sensitivity
|(D+)–(D–)|
–
0.2
V
Vcm
Differential input common mode range
0.8
–
2.5
V
Vse
Single ended receiver threshold
0.8
–
2
V
Rps2
PS/2 pull-up resistance
In PS/2 mode, with PS/2 pull-up
enabled
3
–
7
k
Rext
External USB series resistor
In series with each USB pin
21.78
(–1%)
22
22.22
(+1%)
Zo
USB driver output impedance
Including Rext
28
–
44
CIN
USB transceiver input capacitance
–
20
pF
IIL
Input leakage current (absolute value) 25 °C, VDDD = 3.0 V
–
2
nA
Table 11-13. USBIO AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Tdrate
Full-speed data rate average bit rate
12 – 0.25%
12
12 +
0.25%
MHz
Tjr1
Receiver data jitter tolerance to next
transition
–8
–
8
ns
Tjr2
Receiver data jitter tolerance to pair
transition
–5
–
5
ns
Tdj1
Driver differential jitter to next transition
–3.5
–
3.5
ns
Tdj2
Driver differential jitter to pair transition
–4
–
4
ns
Tfdeop
Source jitter for differential transition to
SE0 transition
–2
–
5
ns
Tfeopt
Source SE0 interval of EOP
160
–
175
ns
Tfeopr
Receiver SE0 interval of EOP
82
–
ns
Tfst
Width of SE0 interval during differential
transition
–
14
ns
Fgpio_out
GPIO mode output operating frequency 3 V
VDDD 5.5 V
–
20
MHz
VDDD = 1.71 V
–
6
MHz
Tr_gpio
Rise time, GPIO mode, 10%/90% VDDD VDDD > 3 V, 25 pF load
1
–
12
ns
VDDD = 1.71 V, 25 pF load
4
–
40
ns
Tf_gpio
Fall time, GPIO mode, 90%/10% VDDD VDDD > 3 V, 25 pF load
1
–
12
ns
VDDD = 1.71 V, 25 pF load
4
–
40
ns
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