參數(shù)資料
型號: CY8C5386AXI-081
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 外設(shè)及接口
英文描述: MULTIFUNCTION PERIPHERAL, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLAINT, MS-026, TQFP-100
文件頁數(shù): 43/102頁
文件大小: 2374K
代理商: CY8C5386AXI-081
PRELIMINARY
PSoC 5: CY8C53 Family Datasheet
Document Number: 001-55035 Rev. *G
Page 45 of 102
Figure 7-19. CAN Controller Block Diagram
7.6 USB
PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0
transceiver supporting all four USB transfer types: control,
interrupt, bulk, and isochronous. The maximum data payload
size is 64 bytes for control, interrupt, and bulk endpoints and
1023 bytes for isochronous. PSoC Creator provides full
configuration support. USB interfaces to hosts through two
dedicated USBIO pins, which are detailed in the “I/O System and
USB includes the following features:
Eight unidirectional data endpoints
One bidirectional control endpoint 0 (EP0)
Shared 512-byte buffer for the eight data endpoints
Dedicated 8-byte buffer for EP0
Three memory modes
Manual Memory Management with No DMA Access
Manual Memory Management with Manual DMA Access
Automatic Memory Management with Automatic DMA
Access
Internal 3.3 V regulator for transceiver
Internal 48 MHz oscillator that auto locks to USB bus clock,
requiring no external crystal for USB (USB equipped parts only)
Interrupts on bus and each endpoint event, with device wakeup
USB Reset, Suspend, and Resume operations
Bus powered and self powered modes
Figure 7-20. USB
TxMessage0
TxReq
TxAbort
TxMessage7
TxReq
TxAbort
TxMessage1
TxReq
TxAbort
TxMessage6
TxReq
TxAbort
Priority
Arbiter
RxMessage0
RxMessage15
RxMessage1
RxMessage14
RxMessage
Handler
Acceptance Code 0
Acceptance Mask 0
Acceptance Code 1
Acceptance Mask 1
Acceptance Code 14
Acceptance Mask 14
Acceptance Code 15
Acceptance Mask 15
RTR RxMessages
0-15
Tx
CAN
Framer
CRC
Generator
Rx
CAN
Framer
CRC Check
Bit Timing
Error Detection
CRC
Form
ACK
Bit Stuffing
Bit Error
Overload
Arbitration
TxInterrupt
Request
(if enabled)
RxInterrupt
Request
(if enabled)
Error Status
Error Active
Error Passive
Bus Off
Tx Error Counter
Rx Error Counter
ErrInterrupt
Request
(if enabled)
WakeUp
Request
Rx Buffer
Status
RxMessage
Available
Tx Buffer
Status
TxReq
Pending
Rx
Tx
S I E
(Serial Interface
Engine)
48 MHz
IMO
Arbiter
512 X 8
SRAM
USB
I/O
D+
D–
Interrupts
Syst
em
Bus
External 22
Resistors
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