參數(shù)資料
型號: D950-CORE
廠商: 意法半導體
元件分類: 數(shù)字信號處理
英文描述: 16-Bit Fixed Point Digital Signal Processor DSP Core
中文描述: 16位定點數(shù)字信號處理器DSP核
文件頁數(shù): 12/89頁
文件大?。?/td> 560K
代理商: D950-CORE
12/89
D950-Core
Data buses (XD/YD and XA/YA) are provided externally. Data memories (RAM, ROM) and
peripherals registers are to be mapped in these address spaces.
Instruction bus (ID/IA) gives access to program memory (RAM, ROM). Each bus has its own
control interface
Table 3.1
Data/Instruction Bus and Corresponding Address Bus.
Depending on the calculation mode, the D950-Core DCU computes operands which can be
considered as 16 or 32-bit, signed or unsigned. It includes a 16 x 16-bit parallel multiplier able
to implement MAC-based functions in one cycle per MAC. A 40-bit arithmetic and logic unit,
including a 8-bit extension for arithmetic operations, implements a wide range of arithmetic
and logic functions. A 40-bit barrel shifter unit and a bit manipulation unit are included.
Tables 3.2 and 3.3 illustrate the different types of word length and word format available for
manipulation.
Table 3.2
Summary of Possible Word Lengths
Data / Instruction Buses
Bidirectional
Bidirectional
Bidirectional
Corresponding Address Bus
Unidirectional
Unidirectional
Unidirectional
XD
YD
ID
16-bit
16-bit
16-bit
XA
YA
IA
16-bit
16-bit
16-bit
0
1-bit word
7
0
8-bit word
15
0
16-bit word signed / unsigned
31 16
15
0
32-bit word signed / unsigned
39 32
31 16
15
0
40-bit word signed / unsigned
Table 3.3
Summary of Possible Word Formats
Format
fractional
Minimum
- 1
0
- 32768
0
Maximum
+ 0.999969481
+ 0.99996948
+ 32767
+ 65535
signed
unsigned
signed
unsigned
integer
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