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參數(shù)資料
| 型號： | D950-CORE |
| 廠商： | 意法半導體 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Fixed Point Digital Signal Processor DSP Core |
| 中文描述： | 16位定點數(shù)字信號處理器DSP核 |
| 文件頁數(shù)： | 18/89頁 |
| 文件大?。?/td> | 560K |
| 代理商： | D950-CORE |
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D950-Core
The ALU output is always made to one of the two accumulators and the CCR (with the
exception of particular ALU codes which affect only CCR or an accumulator). The ALU
operations can be partitioned into three different groups (see
Section 5.4.2
), depending on the
number of operands the operation requires:
Specific ALU codes (see
Section 5.4.2
) are used to implement a non-restoring conditional
add/subtract division algorithm. The division can be signed or unsigned. The dividend must be
a 32-bit operand sign extended to 40-bit and located in the 40-bit accumulator. The divisor
must be a 16-bit operand located in R0 or R1 (LR-bit of STA register must be low).
In order to obtain a valid result, the absolute value of the dividend must be strictly smaller than
the absolute value of the divisor (considering operand is in a fractional format).
Special features are implemented in the D950-Core to process multi-precision data (see
DMULT instruction for double-precision MAC operations).
Two overflow preventions exist in the D950-Core (see SAT and ES bits of STA register):
1: For the multiplier, when multiplying 0x8000 by 0x8000 in signed/signed fraction-
al mode, the saturation block forces the multiplier result to 0x7FFFFFFF,
2: For the ALU, when the result overflows. Provided one of the two optional satu-
ration modes (32-bit saturation or 40-bit saturation) has been selected, the ac-
cumulator destination is set to plus or minus the maximum value.
Two rounding operations are enabled in the D950-Core (see RND-bit of STA register):
1: The multiplier result stored in P register explicitly defined by the instruction. A
two’s complement rounding is performed on the result which is stored in the 16-
bit PH register (see
Section 5.4.2
).
2: The 40-bit accumulator (either two’s complement or convergent rounding) pro-
vided by ALU operation (see RND-bit of STA register).
4.1.6 Bit Manipulation Unit (BMU)
The BMU allows bit manipulation operations on 16-bit data sources, accessed in 3 different
modes: direct, indirect and register addressing, through dedicated instructions.
An 8-bit mask is applied to enable the following operations on a bit-per-bit basis:
TSTL: bit test low.
TSTH: bit test high.
TSTHSET: bit test high and set.
TSTLCLR: bit test low and reset.
ALU Code
3 operands
2 operands
1 operand
Number of Sources
2
1
1 (source=destination)
Number of Destinations
1
1
1 (source=destination)
5
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| D950N | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Netz-Gleichrichterdiode Rectifier Diode |
| D950N18T | 功能描述:整流器 Rectifier Diode 950A 1800V RoHS:否 制造商:Vishay Semiconductors 產品:Standard Recovery Rectifiers 配置: 反向電壓:100 V 正向電壓下降: 恢復時間:1.2 us 正向連續(xù)電流:2 A 最大浪涌電流:35 A 反向電流 IR:5 uA 安裝風格:SMD/SMT 封裝 / 箱體:DO-221AC 封裝:Reel |
| D-951-10 | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:NylaKrimp? Funnel Entry Ring Tongue Terminal for 8 AWG Wire, Stud #5 |
| D-951-14 | 制造商:ETC MOLEX-INACTIVE 功能描述:Cross Referenced to MOLEX - Part: MOL19067-0018 |
| D-951-38 | 制造商:ETC MOLEX-INACTIVE 功能描述:Cross Referenced to MOLEX - Part: MOL19067-0022 |
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