參數(shù)資料
型號(hào): D950-CORE
廠商: 意法半導(dǎo)體
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-Bit Fixed Point Digital Signal Processor DSP Core
中文描述: 16位定點(diǎn)數(shù)字信號(hào)處理器DSP核
文件頁數(shù): 74/89頁
文件大?。?/td> 560K
代理商: D950-CORE
74/89
D950-Core
For the following examples, ‘-’ means RESERVED (read: 0, write: don't care)
15
14
13
12
11
10
9
IS7
IM7
IS6
IM6
IS5
IM5
IS4
IMi:
Interrupt Mask
0: Interrupt i is not masked
1: Interrupt i is masked (def.)
ISi:
Sensitivity
0: ITRQi is active on a low level (def.)
1: ITRQi is active on a falling edge
IPR: Interrupt Priority Register
IPR contains the priority level of each ITRQi interrupt input.
Interrupt priority level is a 2-bit value, so can be 0,1,2 or 3 (0 lowest priority, 3 highest priority).
When two ITRQi of same priority level are requested during the same cycle, the first
acknowledged interrupt is the interrupt corresponding to the lowest numberical value.
After reset, IPR default value is 0.
IPi:
Interrupt Priority level (0, 1, 2 or 3) (def. 0)
ICR: Interrupt Control Register
ICR displays the current priority level and up to four stacked priority levels.
The current priority level is coded using 3 bits but only five different values are available:
Note:
The D950-Core interrupts (SWI, RESET) are priority level 4 (highest level).
An interrupt request is acknowledged when its priority level is strictly higher than the current
priority level. In this case, the current priority level becomes the interrupt priority level and the
previous current priority level is pushed onto the stack and displayed as SPL1.
8
7
6
5
4
3
2
1
0
IM4
IS3
IM3
IS2
IM2
IS1
IM1
IS0
IM0
15 - 14
IP7
13 - 12
IP6
11 - 10
IP5
9 - 8
IP4
7 - 6
IP3
5 - 4
IP2
3 - 2
IP1
1 - 0
IP0
PRIORITY LEVEL
- 1
0
1
2
3
Reserved
CODING
111
000
001
010
011
100 - 110
ACCEPTABLE IT LEVEL PRIORITY
0,1,2,3
1,2,3
2,3
3
8
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