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參數(shù)資料
| 型號(hào)： | D950-CORE |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-Bit Fixed Point Digital Signal Processor DSP Core |
| 中文描述： | 16位定點(diǎn)數(shù)字信號(hào)處理器DSP核 |
| 文件頁(yè)數(shù)： | 76/89頁(yè) |
| 文件大小： | 560K |
| 代理商： | D950-CORE |
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D950-Core
ISPR Interrupt Stack Pointer Register
ISPR contains the number of stacked priority levels. If the ISPR value is directly written, the
SPLi/CPL values are modified. So the ICR register content is no longer significant but the
interrupt routine procedure is not affected. After reset, ISPR default value is 0.
ISPR:
Number of stacked priority levels (0, 1, 2 or 3)
Note:
’-’ is RESERVED (read: 0, write: don't care)
ISR Interrupt Status Register
ISR contains the eight interrupt pending bits, each being associated to one ITRQi interrupt
input.
IPEi-bit is set when the interrupt request is recorded and is reset when the interrupt request is
acknowledged (ITACK falling edge).
An interrupt request will not be acknowledged when IPEi-bit is reset by direct register write.
An interrupt request will be generated whatever the state of ITRQi when IPEi-bit is set by a
direct register write.
When only some pending interrupt requests need to be acknowledged, the IPEi bits of the
other ITRQi interrupt inputs must be reset.
When none of the pending interrupt requests need to be acknowledged, the IPE-bit of CCR
register must be first reset and ISR must be reset.
When IMi-bit is set, the corresponding IPEi-bit is reset. After reset, ISR default value is 0.
IPEi:
Interrupt Pending bit
0: Reset when interrupt request is acknowledged (def.)
1: Set when interrupt request is recorded
Note:
‘
-’ is RESERVED (read: 0, write: don't care)
15
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14
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-
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11
-
10
-
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-
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-
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-
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-
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-
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-
2 - 1 - 0
ISPR
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-
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-
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2
1
0
IPE7 IPE6 IPE5 IPE4 IPE3 IPE2 IPE1 IPE0
8
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