參數(shù)資料
型號: DAC1208D750HN
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
中文描述: SERIAL INPUT LOADING, 0.02 us SETTLING TIME, 12-BIT DAC, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
文件頁數(shù): 25/98頁
文件大小: 554K
代理商: DAC1208D750HN
DAC1208D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 6 December 2010
25 of 98
NXP Semiconductors
DAC1208D750
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
10.4 Clock input
The DAC1208D750 has one differential clock input, CLKINN/CLKINP.
The DAC1208D750 can operate with a clock frequency up to 312.5 MHz or up to 750 MHz
if the internal PLL is bypassed. The clock input can be LVDS (see
Figure 15
) but it can
also be interfaced with CML (see
Figure 16
). Error free data transition from one internal
clock domain to another one is handled by Clock Domain Interface (CDI) logic.
During the reset phase (RESET_N asserted), the clock must be stable and running. This
ensures a proper reset of the complete device.
The device has no embedded power-on-reset feature. Driving the RESET_N pin to set the
device to its default state is mandatory.
Fig 15. LVDS clock configuration
Fig 16. Interfacing CML to LVDS
001aah021
100
Ω
LVDS
CLKINP
CLKINN
LVDS
Z
diff
= 100
Ω
001aah020
55
Ω
55
Ω
1.1 k
Ω
2.2 k
Ω
100 nF
CML
100 nF
100 nF
CLKINP
LVDS
CLKINN
AGND
V
DDA(1V8)
1 k
Ω
Z
diff = 100
Ω
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DAC1208D750HN Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
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