參數(shù)資料
型號: DAC1208D750HN
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
中文描述: SERIAL INPUT LOADING, 0.02 us SETTLING TIME, 12-BIT DAC, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
文件頁數(shù): 51/98頁
文件大?。?/td> 554K
代理商: DAC1208D750HN
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10.15.2.5
Page 2 allocation map description
D
A
P
R
5
N
D
2
×
,
×
×
Table 59.
Address Register name
Page 2 register allocation map
R/W
Bit definition
b7
-
Default
Bin
00000011 03h
b6
b5
FULL_RE_
INIT
b4
SYNC_INIT_
LEVEL
b3
b2
b1
FORCE_
RESET_
DCLK
FCLK_SEL[1:0]
b0
FORCE_
RESET_
FCLK
Hex
0
00h MAINCONTROL
R/W
-
0
0
3
4
5
6
7
8
9
22 16h SET_VCM_VOLTAGE R/W
23 17h SET_SYNC
27 1Bh TYPE_ID
28 1Ch DAC_VERSION
29 1Dh DIG_VERSION
30 1Eh JRX_ANA_VERSION R
31 1Fh PAGE_ADDRESS
03h JCLK_CNTRL
04h RST_EXT_FCLK
05h RST_EXT_DCLK
06h DCSMU_PREDIVCNT R/W
07h PLL_CHARGETIME
08h PLL_RUN_IN_TIME
09h CA_RUN_IN_TIME
R/W
R/W
R/W
SR_CDI
-
CDI_MODE[1:0]
RST_EXT_FCLK_TIME[7:0]
RST_EXT_DCLK_TIME[7:0]
DCSMU_PREDIVIDER[7:0]
PLL_CHARGE_TIME[7:0]
PLL_RUNIN_TIME[7:0]
CA_RUNIN_TIME[7:0]
-
-
SET_SYNC_VCOM[2:0]
FRONTEND[1:0]
DAC_VERSION_ID[7:0]
DIG_VERSION_ID[7:0]
JRX_ANA_VERSION_ID[7:0]
-
-
-
FCLK_POL
00000000 00h
00111111
00100000 20h
00011110 1Eh
00110010 32h
00110010 32h
00000100 04h
00000010 02h
01000011 43h
11011110 DEh
00000001 01h
00000010 02h
00000010 02h
00000000 00h
3Fh
R/W
R/W
R/W
-
-
-
SET_VCM[3:0]
SET_SYNC_LEVEL[2:0]
R/W
R
R
R
-
DAC
DUAL
DSP
BIT_RES[1:0]
R/W
-
-
-
PAGE[2:0]
相關(guān)PDF資料
PDF描述
DAC1208D750HN Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
DL-5538S-C550-SB 1270 nm ~ 1610 nm DFB LD MODULES 2.5 Gbps CWDM MQW-DFB LD RECEPTACLE
DL-5538S-C450-FB 1270 nm ~ 1610 nm DFB LD MODULES 2.5 Gbps CWDM MQW-DFB LD RECEPTACLE
DL-5538S-C450-S 1270 nm ~ 1610 nm DFB LD MODULES 2.5 Gbps CWDM MQW-DFB LD RECEPTACLE
DL-5538S-C450-SB 1270 nm ~ 1610 nm DFB LD MODULES 2.5 Gbps CWDM MQW-DFB LD RECEPTACLE
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