參數(shù)資料
型號: DAC1208D750HN
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
中文描述: SERIAL INPUT LOADING, 0.02 us SETTLING TIME, 12-BIT DAC, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
文件頁數(shù): 98/98頁
文件大?。?/td> 554K
代理商: DAC1208D750HN
NXP Semiconductors
DAC1208D750
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 December 2010
Document identifier: DAC1208D750
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.5.1 Single device operation . . . . . . . . . . . . . . . . . 15
10.2.5.2 Multi-device operation . . . . . . . . . . . . . . . . . . 15
10.2.5.3 Master/slave mode . . . . . . . . . . . . . . . . . . . . . 17
10.2.5.4 All slave mode . . . . . . . . . . . . . . . . . . . . . . . . 20
10.2.6
Frame assembly. . . . . . . . . . . . . . . . . . . . . . . 21
10.3
Serial Peripheral Interface (SPI). . . . . . . . . . . 23
10.3.1
Protocol description . . . . . . . . . . . . . . . . . . . . 23
10.3.2
SPI timing description. . . . . . . . . . . . . . . . . . . 24
10.4
Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.5
FIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
10.6
Quadrature modulator and Numerically
Controlled Oscillator (NCO) . . . . . . . . . . . . . . 27
10.6.1
NCO in 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.6.2
Low-power NCO. . . . . . . . . . . . . . . . . . . . . . . 27
10.6.3
Minus_3dB . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.7
x / (sin x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.8
DAC transfer function . . . . . . . . . . . . . . . . . . . 28
10.9
Full-scale current . . . . . . . . . . . . . . . . . . . . . . 29
10.9.1
Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.9.1.1 External regulation . . . . . . . . . . . . . . . . . . . . . 29
10.9.2
Full-scale current adjustment . . . . . . . . . . . . . 29
10.10
Digital offset correction. . . . . . . . . . . . . . . . . . 30
10.11
Analog output . . . . . . . . . . . . . . . . . . . . . . . . . 31
10.12
Auxiliary DACs . . . . . . . . . . . . . . . . . . . . . . . . 32
10.13
Output configuration . . . . . . . . . . . . . . . . . . . . 33
10.13.1
Basic output configuration . . . . . . . . . . . . . . . 33
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal characteristics . . . . . . . . . . . . . . . . . . 6
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Application information. . . . . . . . . . . . . . . . . . 11
General description . . . . . . . . . . . . . . . . . . . . 11
JESD204A receiver . . . . . . . . . . . . . . . . . . . . 12
Lane input. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Sync and word align . . . . . . . . . . . . . . . . . . . . 13
Comma detection and word align. . . . . . . . . . 14
Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Inter-lane alignment . . . . . . . . . . . . . . . . . . . . 15
10.13.2
DC interface to an Analog Quadrature
Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . 34
AC interface to an Analog Quadrature
Modulator (AQM) . . . . . . . . . . . . . . . . . . . . . . 36
Phase correction . . . . . . . . . . . . . . . . . . . . . . 37
Power and grounding. . . . . . . . . . . . . . . . . . . 37
Configuration interface. . . . . . . . . . . . . . . . . . 37
Register description. . . . . . . . . . . . . . . . . . . . 37
Detailed descriptions of registers. . . . . . . . . . 37
10.15.2.1 Page 0 allocation map description. . . . . . . . . 38
10.15.2.2 Page 0 bit definition detailed description . . . . 40
10.15.2.3 Page 1 allocation map description. . . . . . . . . 46
10.15.2.4 Page 1 bit definition detailed description . . . . 47
10.15.2.5 Page 2 allocation map description. . . . . . . . . 51
10.15.2.6 Page 2 bit definition detailed description . . . . 52
10.15.2.7 Page 4 allocation map description. . . . . . . . . 56
10.15.2.8 Page 4 bit definition detailed description . . . . 58
10.15.2.9 Page 5 allocation map description. . . . . . . . . 68
10.15.2.10 Page 5 bit definition detailed description . . . 70
10.15.2.11 Page 6 allocation map description . . . . . . . . 77
10.15.2.12 Page 6 bit definition detailed description . . . 79
10.15.2.13 Page 7 allocation map description . . . . . . . . 83
10.15.2.14 Page 7 bit definition detailed description . . . 85
11
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 89
12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 90
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . 91
14
Legal information . . . . . . . . . . . . . . . . . . . . . . 92
14.1
Data sheet status. . . . . . . . . . . . . . . . . . . . . . 92
14.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
14.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 92
14.4
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 93
15
Contact information . . . . . . . . . . . . . . . . . . . . 93
16
Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
17
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
10.13.3
10.13.4
10.14
10.15
10.15.1
10.15.2
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