參數(shù)資料
型號: DAC1208D750HN
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
中文描述: SERIAL INPUT LOADING, 0.02 us SETTLING TIME, 12-BIT DAC, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
文件頁數(shù): 41/98頁
文件大?。?/td> 554K
代理商: DAC1208D750HN
DAC1208D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 6 December 2010
41 of 98
NXP Semiconductors
DAC1208D750
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
1 to 0
INT_FIR[1:0]
R/W
interpolation
no interpolation
2
×
4
×
8
×
00
01
10
11
Table 19.
Default settings are shown highlighted.
Bit
Symbol
TXCFG register (address 01h) bit description
…continued
Access
Value
Description
Table 20.
Default settings are shown highlighted.
Bit
Symbol
7
PLL_PD
PLLCFG register (address 02h) bit description
Access
R/W
Value
Description
PLL
switched on
switched off
undefined
must be written with ’0’
PLL divider factor
2
4
8
PLL phase shift of f
s
0
°
120
°
240
°
undefined
clock edge of DAC (f
s
)
normal
inverted
0
1
0
0
6
5
4 to 3
-
-
PLL_DIV[1:0]
R/W
R/W
R/W
00
01
10
2 to 1
PLL_PHASE[1:0]
R/W
00
01
10
11
0
PLL_POL
R/W
0
1
Table 21.
Bit
7 to 0
FREQNCO_LSB register (address 03h) bit description
Symbol
FREQ_NCO[7:0]
Access
R/W
Value
66h
Description
lower 8 bits for the NCO frequency setting
Table 22.
Bit
7 to 0
FREQNCO_LISB register (address 04h) bit description
Symbol
FREQ_NCO[15:8]
Access
R/W
Value
66h
Description
lower intermediate 8 bits for the NCO frequency
setting
Table 23.
Bit
7 to 0
FREQNCO_UISB register (address 05h) bit description
Symbol
FREQ_NCO[23:16]
Access
R/W
Value
66h
Description
upper intermediate 8 bits for the NCO frequency
setting
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DAC1208D750HN Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
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