參數(shù)資料
型號: DAC1208D750HN
廠商: NXP SEMICONDUCTORS
元件分類: DAC
英文描述: Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
中文描述: SERIAL INPUT LOADING, 0.02 us SETTLING TIME, 12-BIT DAC, PQCC64
封裝: 9 X 9 MM, 0.85 MM HEIGHT, PLASTIC, SOT804-3, VQFN-64
文件頁數(shù): 40/98頁
文件大?。?/td> 554K
代理商: DAC1208D750HN
DAC1208D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 6 December 2010
40 of 98
NXP Semiconductors
DAC1208D750
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
10.15.2.2
Page 0 bit definition detailed description
Please refer to
Table 17
for a register overview for page 0. In the following tables, all the
values emphasized in bold are the default values.
Table 18.
Default settings are shown highlighted.
Bit
Symbol
7
SPI_3W
COMMON register (address 00h) bit description
Access
R/W
Value
Description
serial interface bus type
4 wire SPI
3 wire SPI
serial interface reset
no reset
performs a reset on all registers except 0x00
data format
signed (two’s compliment) format
unsigned format
power-down
no action
all circuits (digital and analog) are switched off
internal band gap power-down
no action
internal band gap references are switched off
0
1
6
SPI_RST
R/W
0
1
2
DF
R/W
0
1
1
PD_ALL
R/W
0
1
0
GAP_PD
R/W
0
1
Table 19.
Default settings are shown highlighted.
Bit
Symbol
7
NCO_EN
TXCFG register (address 01h) bit description
Access
R/W
Value
Description
NCO
disabled (the NCO phase is reset to 0)
enabled
low-power NCO
NCO may use all 32 bits
NCO frequency and phase given by the five
MSBs of the registers 06h and 08h respectively
x / (sin x) function
disabled
enabled
modulation
dual DAC: no modulation
positive upper single sideband up-conversion
positive lower single sideband up-conversion
negative upper single sideband up-conversion
negative lower single sideband up-conversion
0
1
6
NCO_LP_SEL
R/W
0
1
5
INV_SINE_EN
R/W
0
1
4 to 2
MODE[2:0]
R/W
000
001
010
011
100
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