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參數(shù)資料
| 型號： | DS1878T+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTLR SFP W/DGTL LDD RX 28TQFN |
| 標準包裝： | 2,500 |
| 類型： | SFP+ 控制器 |
| 輸入類型： | 模擬，數(shù)字 |
| 輸出類型： | 數(shù)字 |
| 接口： | I²C，LDD，串行 |
| 電流 - 電源： | 2.5mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
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DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________
17
Right-Shifting ADC Result
If the weighting of the ADC digital reading must con-
form to a predetermined full-scale (PFS) value defined
by a standard’s specification (e.g., SFF-8472), then
right-shifting can be used to adjust the PFS analog
measurement range while maintaining the weighting of
the ADC results. The device’s range is wide enough to
cover all requirements; when the maximum input value
is
≤ 1/2 of the FS value, right-shifting can be used to
obtain greater accuracy. For instance, the maximum
voltage might be 1/8 the specified PFS value, so only
1/8 the converter’s range is effective over this range.
An alternative is to calibrate the ADC’s full-scale range
to 1/8 the readable PFS value and use a right-shift
value of 3. With this implementation, the resolution of
the measurement is increased by a factor of 8, and
because the result is digitally divided by 8 by right-
shifting, the bit weight of the measurement still meets
the standard’s specification (i.e., SFF-8472).
The right-shift operation on the ADC result is carried out
based on the contents of right-shift control registers
(Table 02h, Registers 8Eh–8Fh) in EEPROM. Three ana-
log channels, MON1–MON3, each have 3 bits allocated
to set the number of right-shifts. Up to seven right-shift
operations are allowed and are executed as a part of
every conversion before the results are compared to
the high-alarm and low-alarm levels, or loaded into their
corresponding measurement registers (Lower Memory,
Registers 64h–6Bh). This is true during the setup of
internal calibration as well as during subsequent data
conversions.
VCC or GND Referenced MON2 Input
The device offers a configurable input for MON2.
MON2 can either be referenced to VCC or GND, as
shown in Figure 6. This enables compatibility with dif-
ferent TOSA monitor diode configurations.
Differential MON3 Input
The device offers a fully differential input for MON3.
This enables high-side monitoring of RSSI, as shown in
Figure 7. This reduces board complexity by eliminating
the need for a high-side differential amplifier or a cur-
rent mirror.
DS1878
MON3P
MON3N
ADC
680
Ω
ROSA
VCC
Figure 7. MON3 Differential Input for High-Side RSSI
MON2
BMD
ADC
VCC
1k
Ω
MON2
BMD
ADC
VCC
1k
Ω
Figure 6. MON2 VCC or GND Reference
TEMP
VCC
MON1
MON2
MON3
MON4
TEMP
ONE ROUND-ROBIN ADC CYCLE
tRR
NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC
IS ABOVE THE VCC ALARM LOW THRESHOLD.
Figure 5. ADC Round-Robin Timing
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