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參數(shù)資料
| 型號(hào)： | DS1878T+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 80/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTLR SFP W/DGTL LDD RX 28TQFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | SFP+ 控制器 |
| 輸入類型： | 模擬，數(shù)字 |
| 輸出類型： | 數(shù)字 |
| 接口： | I²C，LDD，串行 |
| 電流 - 電源： | 2.5mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
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Note 1:
All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative.
Note 2:
Inputs are at supply rail. Outputs are not loaded.
Note 3:
Eight ranges allow the full-scale range to change from 312mV to 1.25V.
Note 4:
The output impedance of the device is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance is 1.5k
Ω.
Note 5:
This parameter is guaranteed by design.
Note 6:
Full-scale is programmable.
Note 7:
A temperature conversion is completed and the MODULATION register value is recalled from the LUT and VCC has been
measured to be above the VCC LO alarm.
Note 8:
The timing is determined by the choice of the SAMPLE RATE setting (see Table 02h, Register 88h).
Note 9:
This specification is the time it takes from MON3 voltage falling below the LLOS trip threshold to LOSOUT asserted high.
Note 10: This specification is the time it takes from MON3 voltage rising above the HLOS trip threshold to LOSOUT asserted low.
Note 11: Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four
steps, the bias current will be within 3% within the time specified by the binary search time. See the
BIAS and MODULA-
TION Control During Power-Up section.
Note 12: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C stan-
dard-mode timing.
Note 13: CB—the total capacitance of one bus line in pF.
Note 14: EEPROM write begins after a STOP condition occurs.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
fSCL
(Note 12)
0
400
kHz
Clock Pulse-Width Low
tLOW
1.3
μs
Clock Pulse-Width High
tHIGH
0.6
μs
Bus-Free Time Between STOP and START
Condition
tBUF
1.3
μs
START Hold Time
tHD:STA
0.6
μs
START Setup Time
tSU:STA
0.6
μs
Data In Hold Time
tHD:DAT
0
0.9
μs
Data In Setup Time
tSU:DAT
100
ns
Rise Time of Both SDA and SCL Signals
tR
(Note 13)
20 + 0.1CB
300
ns
Fall Time of Both SDA and SCL Signals
tF
(Note 13)
20 + 0.1CB
300
ns
STOP Setup Time
tSU:STO
0.6
μs
Capacitive Load for Each Bus Line
CB
400
pF
EEPROM Write Time
tWR
(Note 14)
20
ms
DS1878
SFP+ Controller with Digital LDD Interface
8
_______________________________________________________________________________________
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +5.5V, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
At +25°C
200,000
EEPROM Write Cycles
At +85°C
50,000
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +5.5V, TA = -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted.) (Figure 19)
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