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參數(shù)資料
| 型號： | DS1878T+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 15/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTLR SFP W/DGTL LDD RX 28TQFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | SFP+ 控制器 |
| 輸入類型： | 模擬，數(shù)字 |
| 輸出類型： | 數(shù)字 |
| 接口： | I²C，LDD，串行 |
| 電流 - 電源： | 2.5mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
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DS1878
is timed (within 500s) to go to 0, at which point the
part is fully functional.
For all device addresses sourced from EEPROM (Table
02h, Register 8Ch), the default device address is A2h
until VCC exceeds POA, allowing the device address to
be recalled from the EEPROM.
Power-On Analog (POA)
POA holds the device in reset until VCC is at a suitable
level (VCC > POA) for the device to accurately measure
with its ADC and compare analog signals with its quick-
trip monitors. Because VCC cannot be measured by the
ADC when VCC is less than POA, POA also asserts the
VCC LO alarm, which is cleared by a VCC ADC conver-
sion greater than the customer-programmable VCC LO
ADC limit. This allows a programmable limit to ensure
that the headroom requirements of the transceiver are
satisfied during a slow power-up. The TXFOUT output
does not latch until there is a conversion above the
VCC LO limit. The POA alarm is nonmaskable. The TXF
output is asserted when VCC is below POA. See the
Low-Voltage Operation section for more information.
Delta-Sigma Outputs (DAC1 and DAC2)
Two delta-sigma outputs are provided, DAC1 and
DAC2. With the addition of an external RC filter, these
outputs provide two 9-bit resolution analog outputs with
the full-scale range set by the input REFIN. Each output
is either manually controlled or controlled using a tem-
perature-indexed LUT. A delta-sigma is a digital output
using pulse-density modulation. It provides much lower
output ripple than a standard digital PWM output given
the same clock rate and filter components. Before tINIT,
the DAC1 and DAC2 outputs are high impedance.
The external RC filter components are chosen based
on ripple requirements, output load, delta-sigma fre-
quency, and desired response time. A recommended
filter is shown in Figure 11.
The device’s delta-sigma outputs are 9 bits. For illustra-
tive purposes, a 3-bit example is provided in Figure 12.
20
______________________________________________________________________________________
DS1878
DAC
3.24k
Ω
3.24k
Ω
0.01
μF
0.01
μF
VOLTAGE OUTPUT
DS1878
DAC
1k
Ω
1k
Ω
0.1
μF
0.1
μF
CURRENT SINK
2k
Ω
SFP+ Controller with Digital LDD Interface
O
1
2
3
4
5
6
7
Figure 12. Delta-Sigma Outputs
Figure 11. Recommended RC Filter for DAC1/DAC2
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