- 您現在的位置：買賣IC網 > PDF目錄1913 > DS1878T+T&R (Maxim Integrated Products)IC CTLR SFP W/DGTL LDD RX 28TQFN PDF資料下載
參數資料
| 型號： | DS1878T+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 27/101頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTLR SFP W/DGTL LDD RX 28TQFN |
| 標準包裝： | 2,500 |
| 類型： | SFP+ 控制器 |
| 輸入類型： | 模擬，數字 |
| 輸出類型： | 數字 |
| 接口： | I²C，LDD，串行 |
| 電流 - 電源： | 2.5mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁
DS1878
SFP+ Controller with Digital LDD Interface
______________________________________________________________________________________
31
sequence or as an indication that the device is not
receiving data.
Byte write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgement
from the slave to the master. The 8 bits transmitted
by the master are done according to the bit-write
definition and the acknowledgement is read using
the bit-read definition.
Byte read: A byte read is an 8-bit information trans-
fer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit-read definition, and the master
transmits an ACK using the bit-write definition to
receive additional data bytes. The master must
NACK the last byte read to terminate communication
so the slave returns control of SDA to the master.
Slave address byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit.
The device responds to two slave addresses. The
auxiliary memory always responds to a fixed I2C
slave address, A0h. The Lower Memory and Tables
00h–08h respond to I2C slave addresses that can
be configured to any value between 00h–FEh using
the DEVICE ADDRESS byte (Table 02h, Register
8Ch). The user also must set the ASEL bit (Table
02h, Register 89h) for this address to be active. By
writing the correct slave address with R/W = 0, the
master indicates it will write data to the slave. If R/W
= 1, the master reads data from the slave. If an
incorrect slave address is written, the device
assumes the master is communicating with another
I2C device and ignores the communications until the
next START condition is sent. If the main device’s
slave address is programmed to be A0h, access to
the auxiliary memory is disabled.
Memory address: During an I2C write operation to
the device, the master must transmit a memory
address to identify the memory location where the
slave is to store the data. The memory address is
always the second byte transmitted during a write
operation following the slave address byte.
I2C Protocol
Writing a single byte to a slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write the
byte of data, and generate a STOP condition.
Remember the master must read the slave’s
acknowledgement during all byte-write operations.
Writing multiple bytes to a slave: To write multiple
bytes to a slave, the master generates a START con-
dition, writes the slave address byte (R/W = 0),
writes the memory address, writes up to 8 data
bytes, and generates a STOP condition. The device
writes 1 to 8 bytes (one page or row) with a single
write transaction. This is internally controlled by an
address counter that allows data to be written to
consecutive addresses without transmitting a memo-
ry address before each data byte is sent. The
address counter limits the write to one 8-byte page
(one row of the memory map). Attempts to write to
additional pages of memory without sending a STOP
condition between pages results in the address
counter wrapping around to the beginning of the
present row.
For example, a 3-byte write starts at address 06h
and writes 3 data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that address-
es 06h and 07h would contain 11h and 22h, respec-
tively, and the third data byte, 33h, would be written
to address 00h.
To prevent address wrapping from occurring, the
master must send a STOP condition at the end of
the page, then wait for the bus-free or EEPROM
write time to elapse. Then the master can generate a
new START condition and write the slave address
byte (R/W = 0) and the first memory address of the
next memory row before continuing to write data.
Acknowledge polling: Any time a EEPROM page is
written, the device requires the EEPROM write time
(tWR) after the STOP condition to write the contents of
the page to EEPROM. During the EEPROM write
time, the device does not acknowledge its slave
address because it is busy. It is possible to take
advantage of that phenomenon by repeatedly
addressing the device, which allows the next page to
be written as soon as the device is ready to receive
the data. The alternative to acknowledge polling is to
wait for maximum period of tWR to elapse before
attempting to write again to the device.
EEPROM write cycles: When EEPROM writes occur,
the device writes the whole EEPROM memory page,
even if only a single byte on the page was modified.
Writes that do not modify all 8 bytes on the page are
allowed and do not corrupt the remaining bytes of
memory on the same page. Because the whole page
is written, bytes on the page that were not modified
during the transaction are still subject to a write
相關PDF資料 |
PDF描述 |
|---|---|
| DS1881Z-050+T&R | IC DGTL POT NV 2CH 45K 16-SOIC |
| DS1882Z-050+T&R | IC POT DIGIT DL LOG 50K 16SOIC |
| DS1884AT+T | IC SFP PON ONU CTRLR 24TQFN |
| DS2105Z+ | IC SCSI TERMINATOR 16-SOIC |
| DS2106S/T&R | IC TERMINATOR SCSI 28-SOIC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DS-187PU | 制造商:Shinagawa Shoko 功能描述: |
| DS-187U | 制造商:Shinagawa Shoko 功能描述: |
| DS1880E-050 | 功能描述:板上安裝溫度傳感器 RoHS:否 制造商:Omron Electronics 輸出類型:Digital 配置: 準確性:+/- 1.5 C, +/- 3 C 溫度閾值: 數字輸出 - 總線接口:2-Wire, I2C, SMBus 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 最大工作溫度:+ 50 C 最小工作溫度:0 C 關閉: 安裝風格: 封裝 / 箱體: 設備功能:Temperature and Humidity Sensor |
| DS1880E-050/T&R | 制造商:Maxim Integrated Products 功能描述:DUAL LOG POT + EQUALIZER T&R - Tape and Reel |
| DS1880E-050/T&R | 功能描述:板上安裝溫度傳感器 RoHS:否 制造商:Omron Electronics 輸出類型:Digital 配置: 準確性:+/- 1.5 C, +/- 3 C 溫度閾值: 數字輸出 - 總線接口:2-Wire, I2C, SMBus 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 最大工作溫度:+ 50 C 最小工作溫度:0 C 關閉: 安裝風格: 封裝 / 箱體: 設備功能:Temperature and Humidity Sensor |
發(fā)布緊急采購，3分鐘左右您將得到回復。