參數(shù)資料
型號(hào): DS2153Q-A7+T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 26/60頁(yè)
文件大?。?/td> 0K
描述: IC TXRX E1 1-CHIP 5V 44-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 500
功能: 單芯片收發(fā)器
接口: E1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 65mA
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
DS2153Q
32 of 60
9 TRANSMIT IDLE REGISTERS
There is a set of five registers in the DS2153Q that can be used to custom tailor the data that is to be
transmitted onto the E1 line, on a channel-by-channel basis. Each of the 32 E1 channels can be forced to
have a user-defined idle code inserted into them.
TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address = 26 to 29 Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TIR1 (26)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TIR2 (27)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TIR3 (28)
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
TIR4 (29)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH32
TIR4.7
Transmit Idle Registers.
0 = do not insert the Idle Code into this channel
CH1
TIR1.0
1 = insert the Idle Code into this channel
Note: If CCR3.5 = 1, then a 0 in the TIRs implies that channel data is to be sourced from TSER and a 1 implies that channel data is to be
sourced from the RSER pin.
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 2A Hex)
(MSB)
(LSB)
TIDR7
TIDR6
TIDR5
TIDR4
TIDR3
TIDR2
TIDR1
TIDR0
SYMBOL
POSITION NAME AND DESCRIPTION
TIDR7
TIDR.7
MSB of the Idle Code
TIDR0
TIDR.0
LSB of the Idle Code
Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represents a time slot in
the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). In the TIDR, the MSB is transmitted first. Via
the CCR3.5 bit, the user has the option to use the TIRs to determine on a channel-by-channel basis, if data
from the RSER pin should be substituted for data from the TSER pin. In this mode, if the corresponding
bit in the TIRs is set to 1, then data will be sourced from the RSER pin. If the corresponding bit in the
TIRs is set to 0, then data for that channel will sourced from the TSER pin. See the Transmit Data Flow
diagram in Section 14 for more details.
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