參數(shù)資料
型號(hào)： DS2153Q-A7+T&R
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 27/60頁(yè)
文件大小： 0K
描述： IC TXRX E1 1-CHIP 5V 44-PLCC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 500
功能： 單芯片收發(fā)器
接口： E1
電路數(shù)： 1
電源電壓： 4.75 V ~ 5.25 V
電流 - 電源： 65mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
DS2153Q
33 of 60
10 CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel
Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins,
respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either
high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD
controller in ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and
TCHCLK pins will be held high during the entire corresponding channel time. See the timing diagrams in
Section 14 for an example. The TCBRs have an alternate mode of use. Via the CCR3.6 bit, the user has
the option to use the TCBRs to determine on a channel by channel basis, which signaling bits are to be
inserted via the TSRs (the corresponding bit in the TCBRs = 1) and which are to be sourced from the
TSER pin (the corresponding bit in the TCBR = 0). See the Transmit Data Flow diagram in Section 14
for more details.
RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING
REGISTERS (Address = 2B to 2E Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RCBR1 (2B)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RCBR2 (2C)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RCBR3 (2D)
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
RCBR4 (2E)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH32
RCBR4.7
Receive Channel Blocking Registers.
0 = force the RCHBLK pin to remain low during this
channel time
CH1
RCBR1.0
1 = force the RCHBLK pin high during this channel time
TCBR1/TCBR2/TCBR3/TCBR4: TRANSMIT CHANNEL BLOCKING
REGISTERS (Address = 22 to 25 Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TCBR1 (22)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TCBR2 (23)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TCBR3 (24)
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
TCBR4 (25)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH32
TCBR4.7
Transmit Channel Blocking Registers.
0 = force the TCHBLK pin to remain low during this
channel time
CH1
TCBR1.0
1 = force the TCHBLK pin high during this channel time
Note: If CCR3.6 = 1, then a 0 in the TCBRs implies that signaling data is to be sourced from TSER and a 1 implies that signaling data for
that channel is to be sourced from the Transmit Signaling (TS) registers.
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