參數(shù)資料
型號： DS2153Q-A7+T&R
廠商： Maxim Integrated Products
文件頁數(shù)： 9/60頁
文件大?。?/td> 0K
描述： IC TXRX E1 1-CHIP 5V 44-PLCC
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 500
功能： 單芯片收發(fā)器
接口： E1
電路數(shù)： 1
電源電壓： 4.75 V ~ 5.25 V
電流 - 電源： 65mA
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應商設備封裝： 44-PLCC（16.59x16.59）
包裝： 帶卷 (TR)
DS2153Q
17 of 60
4.1 Local Loopback
When CCR2.0 is set to a 1, the DS2153Q will be forced into Local Loopback (LLB). In this loopback,
data will continue to be transmitted as normal through the transmit side of the SCT. Data being received
at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass
through the jitter attenuator. See Figure 1-1 for more details.
4.2 Remote Loopback
When CCR2.1 is set to a 1, the DS2153Q will be forced into Remote Loopback (RLB). In this loopback,
data recovered off the E1 line from the RTIP and RRING pins will be transmitted back onto the E1 line
(with any BPVs that might have occurred intact) via the TTIP and TRING pins. Data will continue to
pass through the receive side of the DS2153Q as it would normally and the data at the TSER input will be
ignored. Data in this loopback will pass through the jitter attenuator. See Figure 1-1 for more details.
4.3 Framer Loopback
When CCR1.7 is set to a 1, the DS2153Q will enter a Framer Loopback (FLB) mode. This loopback is
useful in testing and debugging applications. In FLB, the DS2153Q will loop data from the transmit side
back to the receive side. When FLB is enabled, the following will occur:
1) Data will be transmitted at TTIP and TRING.
2) Data off the E1 line at RTIP and RRING will be ignored.
The RCLK output will be replaced with the TCLK input.
4.4 Automatic Alarm Generation
When either CCR2.4 or CCR2.5 is set to 1, the DS2153Q monitors the receive side to determine if any of
the following conditions are present: loss of receive frame synchronization, AIS alarm (all 1s) reception,
or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the
DS2153Q will either force an AIS alarm (if CCR2.5 = 1) or a Remote Alarm (CCR2.4 = 1) to be
transmitted via the TTIP and TRING pins. It is an illegal state to have both CCR2.4 and CCR2.5 set to 1
at the same time.
4.5
Power-Up Sequence
On power-up, after the supplies are stable, the DS2153Q should be configured for operation by writing to
all of the internal registers (this includes setting the Test Register) since the contents of the internal
registers cannot be predicted on power-up. Next, the LIRST bit should be toggled from 0 to 1 to reset the
line interface circuitry (it will take the DS2153Q about 40ms to recover from the LIRST being toggled).
Finally, after the SYSCLK input is stable, the ESR bit should be toggled from a 0 to a 1 and back to 0
(this step can be skipped if the elastic stores are disabled).
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