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參數資料
| 型號： | DS2153Q-A7+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 35/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX E1 1-CHIP 5V 44-PLCC |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 500 |
| 功能： | 單芯片收發(fā)器 |
| 接口： | E1 |
| 電路數： | 1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 電流 - 電源： | 65mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應商設備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
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DS2153Q
40 of 60
13.1 Receive Clock and Data Recovery
The DS2153Q contains a digital clock recovery system. See Figure 1-1 and Figure 13-1 for more details.
The DS2153Q couples to the receive E1 twisted pair or coax via a 1:1 transformer. See Table 13-3 for
transformer details. The DS2153Q automatically adjusts to the E1 signal being received at the RTIP and
RRING pins and can handle E1 twisted pair cables of 0.6mm (22 AWG) from 0 to 1.5km in length. The
crystal attached at the XTAL1 and XTAL2 pins is multiplied by 4 via an internal PLL and fed to the
clock recovery system. The clock recovery system uses both edges of the clock from the PLL circuit to
form a 32 times oversampler that is used to recover the clock and data. This oversampling technique
offers outstanding jitter tolerance (see Figure 13-2).
Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI waveform
presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING, a Receive
Carrier Loss (RCL) condition will occur and the RCLK can be sourced from either the ACLKI pin or
from the crystal attached to the XTAL1 and XTAL2 pins. The DS2153Q will sense the ACLKI pin to
determine if a clock is present. If no clock is applied to the ACLKI pin, then it should be tied to RVSS to
prevent the device from falsely sensing a clock. See Table 13-1. If the jitter attenuator is either placed in
the transmit path or is disabled, the RCLK output can exhibit short high cycles of the clock. This is due to
the highly oversampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path
(as is the case in most applications), the jitter attenuator restores the RCLK to being close to 50% duty
cycle. See the receive AC timing characteristics in Section 16 for more details.
Table 13-1. Source of RCLK Upon RCL
ACLKI PRESENT?
RECEIVE SIDE JITTER
ATTENUATOR
TRANSMIT SIDE JITTER
ATTENUATOR
Yes
ACLKI via the jitter attenuator
ACLKI
No
Centered crystal
TCLK via the jitter attenuator
相關PDF資料 |
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| DS2154LNA2+ | IC TXRX E1 5V 100-LQFP |
| DS2154L | IC TXRX E1 1CHIP 5V ENH 100-LQFP |
| DS2155LN | IC TXRX T1/E1/J1 1-CHIP 100-LQFP |
| DS2156LN+ | IC TXRX T1/E1/J1 1-CHIP 100-LQFP |
| DS2172T/T&R | IC TESTER BIT ERROR RATE 32-TQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DS2153QN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver |
| DS2153QN-A5 | 功能描述:IC TXRX E1 1-CHIP 5V IND 44-PLCC RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS 產品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| DS2153QN-A7 | 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2153QN-A7/T&R | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS2153QN-A7/T&R+ | 制造商:Maxim Integrated Products 功能描述:FRAMER E1/ISDN-PRI/PCM-30 5V 44PLCC - Tape and Reel |
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