參數(shù)資料
型號: DS2153Q-A7+T&R
廠商: Maxim Integrated Products
文件頁數(shù): 3/60頁
文件大?。?/td> 0K
描述: IC TXRX E1 1-CHIP 5V 44-PLCC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準包裝: 500
功能: 單芯片收發(fā)器
接口: E1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 65mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
DS2153Q
11 of 60
Table 4-1. Sync/Resync Criteria
FRAME OR
MULTIFRAME
LEVEL
SYNC CRITERIA
RESYNC CRITERIA
ITU SPEC
FAS
FAS present in frames N
and N + 2, and FAS not
present in frame N + 1.
Three consecutive incorrect FAS received.
Alternate (RCR1.2 = 1) the above criteria
is met or three consecutive incorrect bit 2
of non-FAS received.
G.706
4.1.1
4.1.2
CRC4
Two valid MF alignment
words found within 8ms.
915 or more CRC4 codewords out of 1000
received in error.
G.706
4.2
4.3.2
CAS
Valid MF alignment word
found and previous time slot
16 contains code other than
all 0s.
Two consecutive MF alignment words
received in error.
G.732
5.2
RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex)
(MSB)
(LSB)
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
RSCLKM
RESE
SYMBOL
POSITION
NAME AND DESCRIPTION
Sa8S
RCR2.7
Sa8 Bit Select. Set to 1 to report the Sa8 bit at the RLINK pin;
set to 0 to not report the Sa8 bit.
Sa7S
RCR2.6
Sa7 Bit Select. Set to 1to report the Sa7 bit at the RLINK pin;
set to 0 to not report the Sa7 bit.
Sa6S
RCR2.5
Sa6 Bit Select. Set to 1 to report the Sa6 bit at the RLINK pin;
set to 0 to not report the Sa6 bit.
Sa5S
RCR2.4
Sa5 Bit Select. Set to 1 to report the Sa5 bit at the RLINK pin;
set to 0 to not report the Sa5 bit.
Sa4S
RCR2.3
Sa4 Bit Select. Set to 1 to report the Sa4 bit at the RLINK pin;
set to 0 to not report the Sa4 bit.
RSCLKM
RCR2.2
Receive Side SYSCLK Mode Select.
0 = if SYSCLK is 1.544MHz
1 = if SYSCLK is 2.048MHz
RESE
RCR2.1
Receive Side Elastic Store Enable.
0=elastic store is bypassed
1=elastic store is enabled
RCR2.0
Not Assigned. Should be set to 0 when written.
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